3.3/55V 1.27mm PMIC MAX® 7000 Series EPM7064 5V 68-LCC (J-Lead)
SOT-23
EPM7064LC68-15 Datasheet
non-compliant
In-Stock: 0 items
Specifications
Name
Value
Type
Parameter
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Surface Mount
YES
Operating Temperature
0°C~70°C TA
Packaging
Tray
Series
MAX® 7000
JESD-609 Code
e0
Part Status
Obsolete
Moisture Sensitivity Level (MSL)
2 (1 Year)
Number of Terminations
68
ECCN Code
EAR99
Terminal Finish
TIN LEAD
Additional Feature
CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
Subcategory
Programmable Logic Devices
Technology
CMOS
Terminal Position
QUAD
Terminal Form
J BEND
Peak Reflow Temperature (Cel)
220
Supply Voltage
5V
Terminal Pitch
1.27mm
Time@Peak Reflow Temperature-Max (s)
30
Base Part Number
EPM7064
JESD-30 Code
S-PQCC-J68
Qualification Status
Not Qualified
Supply Voltage-Max (Vsup)
5.25V
Power Supplies
3.3/55V
Programmable Type
EE PLD
Number of I/O
52
Clock Frequency
100MHz
Propagation Delay
15 ns
Number of Gates
1250
Output Function
MACROCELL
Number of Macro Cells
64
JTAG BST
NO
Voltage Supply - Internal
4.75V~5.25V
Delay Time tpd(1) Max
15ns
Number of Logic Elements/Blocks
4
Height Seated (Max)
5.08mm
RoHS Status
Non-RoHS Compliant
Pricing & Ordering
Quantity
Unit Price
Ext. Price
1
$1.386520
$1.38652
10
$1.308037
$13.08037
100
$1.233997
$123.3997
500
$1.164149
$582.0745
1000
$1.098253
$1098.253
EPM7064LC68-15 Product Details
EPM7064LC68-15 Overview
This network has 64macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).You can find it in package 68-LCC (J-Lead).As a result, it has 52 I/O ports programmed.68 terminations have been programmed into the device.Its terminal position is QUAD.It is powered by a voltage of 5V volts.This part is part of the family Programmable Logic Devices.Package the chip by Tray.In order to ensure the reliability of the device, it is designed to operate at a temperature of [0].Chips should be mounted by Surface Mount.In terms of FPGAs, it belongs to the MAX® 7000 series.This device can also display CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V.Its related parts can be found in the [0].The 1250 gates serve as building blocks for digital circuits.This logic block consists of 4 logic elements.A total of 3.3/55V power supplies are needed to run it.5.25V represents the maximal supply voltage (Vsup).This device should not have an clock frequency greater than 100MHz.
EPM7064LC68-15 Features
68-LCC (J-Lead) package 52 I/Os The operating temperature of 0°C~70°C TA 3.3/55V power supplies
EPM7064LC68-15 Applications
There are a lot of Intel EPM7064LC68-15 CPLDs applications.