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ICS673M-01LF

ICS673M-01LF

ICS673M-01LF

Integrated Device Technology (IDT)

3.3V Clock Generators 16 Pins SOIC 16 Terminals

SOT-23

ICS673M-01LF Datasheet

non-compliant

In-Stock: 0 items
Specifications
Name Value
Type Parameter
Package / Case SOIC
Surface Mount YES
Number of Pins 16
Published 1999
JESD-609 Code e3
Pbfree Code yes
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 16
ECCN Code EAR99
Terminal Finish Matte Tin (Sn) - annealed
HTS Code 8542.39.00.01
Technology CMOS
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Number of Functions 1
Supply Voltage 3.3V
Terminal Pitch 1.27mm
Time@Peak Reflow Temperature-Max (s) 30
Pin Count 16
Qualification Status Not Qualified
Operating Temperature (Max) 70°C
Supply Voltage-Max (Vsup) 5.5V
Temperature Grade COMMERCIAL
Supply Voltage-Min (Vsup) 3.13V
Family 673
Output Characteristics 3-STATE
Logic IC Type PLL BASED CLOCK DRIVER
fmax-Min 120 MHz
Same Edge Skew-Max (tskwd) 0.5 ns
Number of True Outputs 2
Input Conditioning STANDARD
Length 9.9mm
Height Seated (Max) 1.75mm
Width 3.9mm
RoHS Status RoHS Compliant
ICS673M-01LF Product Details

ICS673M-01LF Overview


As part of the SOIC package, this clock generator is embedded. This clock generator ic can sustain 260 degrees of temperature during reflowing. There are 16 terminations found in this file. To operate this time clock generator, 3.3V voltage should be applied. 5.5V would be the maximum supply voltage for this clock generator. In order to maintain safety, this frequency generator should be supplied with voltages above 3.13V. In addition, the PLL may cause ha70°Cards once the temperature is set higher than 70°C. It is a 16-bit clock PLL designed specifically for microprocessors. There are 16 pins on the frequency generators that are available for use. Low timing skew is offered by this RF synthesizer at maximum 0.5 ns. The digital clock generator has 2 high-enable output pins. By searching for parts that belong to the 673 family, you can find electronic parts that are similar. PLL BASED CLOCK DRIVER logic circuits are primarily constructed using this time clock generator. Physical input clock PLLs can be used to make control signals using the STANDARD input conditioning feature.

ICS673M-01LF Features


Available in the SOIC
Supply voltage of 3.3V
2 true outputs


ICS673M-01LF Applications


There are a lot of Integrated Device Technology (IDT)
ICS673M-01LF Clock Generators applications.


  • Wireless base station for LTE, LTE-advanced
  • Picocells, femtocells and small cells
  • Sampling clocks for ADC and DAC
  • 1 Gigabit Ethernet
  • 10 Gigabit Ethernet
  • FPGA and processor clocks
  • Line cards used in telephone exchange
  • Fiber Channel
  • PCI express cards
  • Infotainment systems

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