SST25VF040B-50-4I-SAE

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Manufacturer part number:SST25VF040B-50-4I-SAE

Manufacturer:Microchip Technology

Description:Surface Mount SST25 Memory IC SST25 Series SST25VF040B 4 Mb kb 5mm mm

Case Package:SOT-23

Datasheet:SST25VF040B-50-4I-SAE Datasheet

RoHs Status:non-compliant

Name	Value
Type	Parameter
Factory Lead Time	10 Weeks
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	8-SOIC (0.154, 3.90mm Width)
Number of Pins	8
Operating Temperature	-40°C~85°C TA
Packaging	Tube
Series	SST25
Published	1998
JESD-609 Code	e3
Part Status	Active
Moisture Sensitivity Level (MSL)	3 (168 Hours)
Number of Terminations	8
Terminal Finish	Matte Tin (Sn) - annealed
Technology	CMOS
Voltage - Supply	2.7V~3.6V
Terminal Position	DUAL
Peak Reflow Temperature (Cel)	260
Number of Functions	1
Terminal Pitch	1.27mm
Time@Peak Reflow Temperature-Max (s)	40
Base Part Number	SST25VF040B
Operating Supply Voltage	3.3V
Supply Voltage-Max (Vsup)	3.6V
Supply Voltage-Min (Vsup)	2.7V
Memory Size	4Mb 512K x 8
Memory Type	Non-Volatile
Clock Frequency	50MHz
Access Time	8 ns
Memory Format	FLASH
Memory Interface	SPI
Organization	4MX1
Write Cycle Time - Word, Page	10μs
Density	4 Mb
Parallel/Serial	SERIAL
Programming Voltage	2.7V
Height	1.75mm
Length	5mm
Width	4mm
Radiation Hardening	No
RoHS Status	ROHS3 Compliant
Lead Free	Lead Free

Quantity	Unit Price	Ext. Price
1	$1.13000	$1.13
500	$1.1187	$559.35
1000	$1.1074	$1107.4
1500	$1.0961	$1644.15
2000	$1.0848	$2169.6
2500	$1.0735	$2683.75

SST25VF040B-50-4I-SAE Description

The SST25VF040B-50-4I-SAE features a four-wire, SPI-compatible interface that allows for a low pin-count package that occupies less board space and ultimately lowers total system costs. The SST25VF040B-50-4I-SAE is enhanced with improved operating frequency and even lower power consumption. SST25VF040B-50-4I-SAE SPI serial Flash memory is manufactured with proprietary, high-performance CMOS SuperFlash® technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.