74AUP1G175GS,132 Overview

It is packaged in the way of 6-XFDFN. D flip flop is embedded in the Tape & Reel (TR) package. Non-Invertedis the output configured for it. It is configured with the trigger Positive Edge. Surface Mountis positioned in the way of this electronic part. With a supply voltage of 0.8V~3.6V volts, it operates. Temperature is set to -40°C~125°C TA. This D latch has the type D-Type. This type of FPGA is a part of the 74AUP series. Its output frequency should not exceed 300MHz. D latch consists of 1 elements. As a result, it consumes 500nA quiescent current and is not affected by external forces. 6terminations have occurred. The object belongs to the 74AUP1G175 family. Power is provided by a 1.1V supply. Its input capacitance is 0.8pFfarads. The electronic device belongs to the AUP/ULP/Vfamily. It is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 6. Its clock edge trigger type is Positive Edge. Flip flops designed with 1bits are used in this part. It is imperative that the supply voltage (Vsup) is maintained above 0.8Vin order to ensure normal operation.

74AUP1G175GS,132 Features

Tape & Reel (TR) package
74AUP series
6 pins
1 Bits

74AUP1G175GS,132 Applications

There are a lot of Nexperia USA Inc. 74AUP1G175GS,132 Flip Flops applications.

• Synchronous counter
• Functionally equivalent to the MC10/100EL29
• Balanced Propagation Delays
• Cold spare funcion
• Bus hold
• Patented noise
• Data transfer
• Clock pulse
• Dynamic threshold performance
• Memory