74LVC1G79GW,125 Overview

5-TSSOP, SC-70-5, SOT-353is the packaging method. D flip flop is embedded in the Tape & Reel (TR) package. This output is configured with Non-Inverted. This trigger is configured to use Positive Edge. It is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 1.65V~5.5V volts. In the operating environment, the temperature is -40°C~125°C TA. There is D-Type type of electronic flip flop associated with this device. The 74LVCseries comprises this type of FPGA. This D flip flop should not have a frequency greater than 500MHz. This process consumes 500μA quiescents. Currently, there are 5 terminations. The 74LVC1G79 family contains this object. A voltage of 1.8V provides power to the D latch. This T flip flop has a capacitance of 5pF farads at the input. LVC/LCX/Zis the family of this D flip flop. This electronic part is mounted in the way of Surface Mount. This board is designed with 5pins on it. Its clock edge trigger type is Positive Edge. This flip flop is designed with 1 Bits. 1 circuits are used to achieve its superior flexibility. With a current output of 50mA , it offers maximum design flexibility. It consumes 100nA of quiescent current without being affected by external factors.

74LVC1G79GW,125 Features

Tape & Reel (TR) package
74LVC series
5 pins
1 Bits

74LVC1G79GW,125 Applications

There are a lot of Nexperia USA Inc. 74LVC1G79GW,125 Flip Flops applications.

• Digital electronics systems
• CMOS Process
• Single Up Count-Control Line
• Bus hold
• Differential Individual
• Computers
• Counters
• Power down protection
• Functionally equivalent to the MC10/100EL29
• Modulo – n – counter