ROMless CPU32 32-Bit Microcontroller M683xx Series MC68332 5V 132-BQFP Bumpered
SOT-23
MC68332ACEH16 Datasheet
non-compliant
In-Stock: 0 items
Specifications
Name
Value
Type
Parameter
Factory Lead Time
10 Weeks
Mounting Type
Surface Mount
Package / Case
132-BQFP Bumpered
Surface Mount
YES
Operating Temperature
-40°C~85°C TA
Packaging
Tray
Series
M683xx
Published
1996
JESD-609 Code
e3
Part Status
Not For New Designs
Moisture Sensitivity Level (MSL)
3 (168 Hours)
Number of Terminations
132
ECCN Code
EAR99
Terminal Finish
Tin (Sn)
HTS Code
8542.31.00.01
Terminal Position
QUAD
Terminal Form
GULL WING
Peak Reflow Temperature (Cel)
245
Supply Voltage
5V
Terminal Pitch
0.635mm
Time@Peak Reflow Temperature-Max (s)
30
Base Part Number
MC68332
JESD-30 Code
S-PQFP-G132
Qualification Status
Not Qualified
Oscillator Type
Internal
Number of I/O
15
Speed
16MHz
RAM Size
2K x 8
Voltage - Supply (Vcc/Vdd)
4.5V~5.5V
uPs/uCs/Peripheral ICs Type
MICROCONTROLLER
Core Processor
CPU32
Peripherals
POR, PWM, WDT
Clock Frequency
16MHz
Program Memory Type
ROMless
Core Size
32-Bit
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Bit Size
32
Has ADC
NO
DMA Channels
NO
PWM Channels
YES
DAC Channels
NO
Address Bus Width
24
External Data Bus Width
16
Length
24.13mm
Height Seated (Max)
4.572mm
Width
24.13mm
RoHS Status
ROHS3 Compliant
Pricing & Ordering
Quantity
Unit Price
Ext. Price
1
$37.31000
$37.31
10
$34.40700
$344.07
25
$32.86120
$821.53
180
$29.38161
$5288.6898
MC68332ACEH16 Product Details
MC68332ACEH16 Description
The MC68332ACEH16 is a highly integrated 32 bit microcontroller that combines powerful peripheral subsystems with high-performance data manipulation capabilities. This MCU is composed of common modules that communicate with one another via a shared intermodule bus (IMB). A 32-bit CPU (CPU32), a system integration module (SIM), a time processing unit (TPU), a queued serial module (QSM), and a 2-Kbyte static RAM module with TPU emulation capability are all included in the MCU (TPURAM).
MC68332ACEH16 Features
32 Bit Architecture
Fully static operation
Trace on change of flow
Central Processing Unit (CPU32)
Virtual Memory Implementation
Upward Object Code Compatible
Selectable Channel Priority Levels
Loop Mode of Instruction Execution
Table Lookup and Interpolate Instruction
New Instructions for controller Applications
Any Channel can Perform Any Time Function
16 Independent Programmable Channels and Pins
Improved Exception Handling for Controller Applications
Each Channel has Six or Eight 16 Bit Parameter Registers
Dedicated Micro-Engine Operating Independently of CPU32
Two Timer Counter Registers with Programmable Prescalers
Each Channel Can Be Synchronized to Either or Both Counters