ROMless CPU32 32-Bit Microcontroller M683xx Series MC68332 5V 132-BQFP Bumpered
SOT-23
MC68332ACEH25 Datasheet
non-compliant
In-Stock: 0 items
Specifications
Name
Value
Type
Parameter
Mounting Type
Surface Mount
Package / Case
132-BQFP Bumpered
Surface Mount
YES
Operating Temperature
-40°C~85°C TA
Packaging
Tray
Series
M683xx
Published
1996
JESD-609 Code
e3
Part Status
Not For New Designs
Moisture Sensitivity Level (MSL)
3 (168 Hours)
Number of Terminations
132
ECCN Code
EAR99
Terminal Finish
Tin (Sn)
HTS Code
8542.31.00.01
Terminal Position
QUAD
Terminal Form
GULL WING
Peak Reflow Temperature (Cel)
245
Supply Voltage
5V
Terminal Pitch
0.635mm
Time@Peak Reflow Temperature-Max (s)
30
Base Part Number
MC68332
JESD-30 Code
S-PQFP-G132
Qualification Status
Not Qualified
Oscillator Type
Internal
Number of I/O
15
Speed
25MHz
RAM Size
2K x 8
Voltage - Supply (Vcc/Vdd)
4.5V~5.5V
uPs/uCs/Peripheral ICs Type
MICROCONTROLLER
Core Processor
CPU32
Peripherals
POR, PWM, WDT
Clock Frequency
25MHz
Program Memory Type
ROMless
Core Size
32-Bit
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Bit Size
32
Has ADC
NO
DMA Channels
NO
PWM Channels
YES
DAC Channels
NO
Address Bus Width
24
External Data Bus Width
16
Length
24.13mm
Height Seated (Max)
4.572mm
Width
24.13mm
RoHS Status
ROHS3 Compliant
Pricing & Ordering
Quantity
Unit Price
Ext. Price
1
$38.11000
$38.11
10
$35.55400
$355.54
25
$34.06400
$851.6
180
$30.87050
$5556.69
MC68332ACEH25 Product Details
Description
A 32-bit microcontroller with high levels of integration called the MC68332ACEH25 combines high-performance data manipulation with robust peripheral subsystems. The MCU is composed of common modules that connect via an intermodule bus (IMB). The quick creation of devices designed for certain uses is made possible by standardization.
The MCU includes a queued serial module (QSM), a 2-Kbyte static RAM module with TPU emulation capability, a 32-bit CPU (CPU32), a system integration module (SIM), a time processor unit (TPU), and a 32-bit CPU (CPU) (TPURAM).
The MCU can directly use an external clock input or synthesize an internal clock signal from an external reference. The standard operation uses a 32.768-kHz reference frequency. The system clock has a maximum frequency of 20.97 MHz. Changes in clock rate are possible during operation thanks to system hardware and software. Changes in clock rate have no impact on the register and memory contents of MCUs because their operation is entirely static.
The HCMOS architecture, which uses high-density complementary metal-oxide semiconductors, reduces the MCU's basic power consumption. The system clock can be turned off to reduce power usage. This functionality is effectively implemented by the low-power stop (LPSTOP) command found in the CPU32 instruction set.
Features
Time Processor Unit (TPU)
— Dedicated Microengine Operating Independently of CPU32
— 16 Independent, Programmable Channels and Pins
— Any Channel can Perform any Time Function
— Two Timer Count Registers with Programmable Prescalers
— Selectable Channel Priority Levels
Queued Serial Module (QSM)
— Enhanced Serial Communication Interface
— Queued Serial Peripheral Interface
— One 8-Bit Dual Function Port
Static RAM Module with TPU Emulation Capability (TPURAM)
— 2-Kbytes of Static RAM
— May be Used as Normal RAM or TPU Microcode Emulation RAM
Central Processing Unit (CPU32)
— 32-Bit Architecture
— Virtual Memory Implementation
— Table Lookup and Interpolate Instruction
— Improved Exception Handling for Controller Applications