MC9S08QE8CLC Description

Although the MC9S08QE8CLC has circuitry to guard against damage from excessive static voltage or electrical fields, it is nevertheless urged that standard safety precautions be used to prevent applying any voltages greater than the circuit's maximum rated voltages. Unused inputs should be connected to the proper logic voltage level (for example, either VSS or VDD), or the pin's programmable pullup resistor should be enabled, to improve operation reliability.

MC9S08QE8CLC Features

• Two low power stop modes

• Reduced power wait mode

• Low power run and wait modes allow peripherals to run while voltage regulator is in standby

• Peripheral clock gating register can disable clocks to unused modules, thereby reducing currents

• Very low power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to real time counter

• Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock

• Low-voltage warning with interrupt

• Low-voltage detection with reset or interrupt

• Illegal opcode detection with reset

• Illegal address detection with reset

• Flash block protection

MC9S08QE8CLC Applications

• Power Management

• Consumer Electronics

• Portable Devices

• Industrial