MC9S12XEG128MAA                        Description

  The MC9S12XE family of microcontrollers is a further development of the S12XD series, including new features that enhance system integrity and greater functionality. These new features include memory protection unit (MPU) and error correction code (ECC) on flash memory, as well as enhanced EEPROM function (EEE), enhanced XGATE, internal filter frequency modulation phase locked loop (IPLL) and enhanced ATD. The E-Series expands the S12X product range to flash memory up to 1MB and adds the IWeiO function to the 208pin version of the flagship product MC9S12XE100. The MC9S12XE series offers all the benefits and efficiency of 16-bit MCU, providing 32-bit performance. It retains the advantages of low cost, power consumption, EMC and code size efficiency currently enjoyed by Freescale's existing 16-bit MC9S12 and S12X MCU series users. S12XE and S12XD series have a high degree of compatibility.

MC9S12XEG128MAA                       Features

Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D2. for the peripheral features that are available on the different family members.

? 16-Bit CPU12X

— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions

(MEM, WAV, WAVR, REV, REVW) which have been removed

— Enhanced indexed addressing

— Access to large data segments independent of PPAGE

? INT (interrupt module)

— Eight levels of nested interrupts

— Flexible assignment of interrupt sources to each interrupt level.

— External non-maskable high priority interrupt (XIRQ)

— Internal non-maskable high priority Memory Protection Unit interrupt

— Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive interrupts

? EBI (external bus interface)(available in 208-Pin and 144-Pin packages only)

— Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces

— Each chip select output can be configured to complete transaction on either the time-out of one

of the two wait state generators or the deassertion of EWAIT signal

? MMC (module mapping control)

? DBG (debug module)

— Monitoring of CPU and/or XGATE busses with tag-type or force-type breakpoint requests

— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information

? BDM (background debug mode)

? MPU (memory protection unit)

— 8 address regions definable per active program task

— Address range granularity as low as 8-bytes

— No write / No execute Protection Attributes

— Non-maskable interrupt on access violation

? XGATE

— Programmable, high performance I/O coprocessor module

— Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states

— Performs logical, shifts, arithmetic, and bit operations on data

— Can interrupt the HCS12X CPU signalling transfer completion

— Triggers from any hardware module as well as from the CPU possible

— Two interrupt levels to service high priority tasks

— Hardware support for stack pointer initialisation

? OSC_LCP (oscillator)

— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal

— Good noise immunity

— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal

— Transconductance sized for optimum start-up margin for typical crystals

? IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)

MC9S12XEG128MAA                         Applications         

? Special Operating Modes

— Special single-chip mode with active background debug mode

— Special test mode (Freescale use only)

Low-power modes:

? System stop modes

— Pseudo stop mode

— Full stop mode with fast wake-up option

? System wait mode

Operating system states

? Supervisor state

? User state