MC9S12XEQ512MAL Description

The MC9S12XEQ512MAL MCU comes from the MC9S12XE-Family of microcontrollers which is a further development of the S12XD-Family including new features for enhanced system integrity and greater functionality. 

MC9S12XEQ512MAL Features

• Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions (MEM, WAV, WAVR, REV, REVW) which have been removed

• Enhanced indexed addressing

• Access to large data segments independent of PPAGE

• Eight levels of nested interrupts

• Flexible assignment of interrupt sources to each interrupt level.

• External non-maskable high priority interrupt (XIRQ)

• Internal non-maskable high-priority Memory Protection Unit interrupt

• Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive interrupts

• Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces

• Each chip select output can be configured to complete the transaction on either the time-out of one of the two wait state generators or the deassertion of the EWAIT signal

MC9S12XEQ512MAL Applications

• General Uses