ROMless Coldfire V2 32-Bit Microcontroller MCF520x Series MCF5206 3.3V 160-BQFP
SOT-23
MCF5206EAB54 Datasheet
non-compliant
In-Stock: 0 items
Specifications
Name
Value
Type
Parameter
Factory Lead Time
10 Weeks
Mounting Type
Surface Mount
Package / Case
160-BQFP
Surface Mount
YES
Operating Temperature
0°C~70°C TA
Packaging
Tray
Series
MCF520x
Published
1999
JESD-609 Code
e3
Part Status
Not For New Designs
Moisture Sensitivity Level (MSL)
3 (168 Hours)
Number of Terminations
160
ECCN Code
3A991.A.2
Terminal Finish
Matte Tin (Sn)
Terminal Position
QUAD
Terminal Form
GULL WING
Peak Reflow Temperature (Cel)
245
Supply Voltage
3.3V
Terminal Pitch
0.65mm
Time@Peak Reflow Temperature-Max (s)
30
Base Part Number
MCF5206
JESD-30 Code
S-PQFP-G160
Supply Voltage-Max (Vsup)
3.6V
Supply Voltage-Min (Vsup)
3V
Oscillator Type
External
Number of I/O
8
Speed
54MHz
RAM Size
8K x 8
Voltage - Supply (Vcc/Vdd)
3V~3.6V
uPs/uCs/Peripheral ICs Type
MICROPROCESSOR, RISC
Core Processor
Coldfire V2
Peripherals
DMA, WDT
Clock Frequency
54MHz
Program Memory Type
ROMless
Core Size
32-Bit
Connectivity
EBI/EMI, I2C, UART/USART
Bit Size
32
Address Bus Width
28
Boundary Scan
YES
Low Power Mode
YES
External Data Bus Width
32
Format
FIXED POINT
Integrated Cache
YES
RoHS Status
ROHS3 Compliant
Pricing & Ordering
Quantity
Unit Price
Ext. Price
1
$27.10000
$27.1
10
$24.99100
$249.91
25
$23.86800
$596.7
120
$21.34083
$2560.8996
MCF5206EAB54 Product Details
MCF5206EAB54 Description
A DRAM controller, timers, parallel and serial interfaces, system integration, and a Version 2 ColdFire core are all included in the MCF5206e integrated microprocessor. The CPU in this thing is an improved version of the ColdFire MCF5206. The MCF5206e has been improved with a larger 4 Kbyte I-cache, an 8 KByte SRAM, a higher frequency, a Multiply Accumulate (MAC) unit, hardware division, and two channels of DMA. A low-cost option is the MCF5206e CPU, which operates at 54MHz and delivers 50 Dhrystone 2.1 MIPs.
MCF5206EAB54 Features
Version 2 ColdFire? Core.
Multiply-Accumulate Module and Hardware Divide Unit.
4 KByte Direct-Mapped Instruction Cache.
8 KByte On-Chip SRAM.
DRAM Controller, supports EDO and page mode DRAMs.
2-channel DMA Controller.
Two Universal Synchronous/Asynchronous Receiver/Transmitters (UART).