MCF52235CAL60                       Description

  MCF52235 is a member of the family of Coldfire reduced instruction set Computing (RISC) microcontrollers. This document provides an overview of the MCF52235 microcontroller family, focusing on its highly integrated and diverse feature set. Based on the second version of the Coldfire kernel, this 32-bit device runs at a frequency of up to 60 MHz and provides high performance and low power consumption. The on-chip memory closely connected to the processor core includes up to 256K bytes of flash memory and 32K bytes of static random access memory (SRAM).

MCF52235CAL60            Features

? V2 ColdFire core providing 56 Dhrystone 2.1 MIPS @ 60

MHz executing out of on-chip Flash memory using

enhanced multiply accumulate (EMAC) and hardware

divider

? Enhanced Multiply Accumulate Unit (EMAC) and

hardware divide module

? Cryptographic Acceleration Unit (CAU) coprocessor

? Fast Ethernet Controller (FEC)

? On-chip Ethernet Transceiver (EPHY)

? FlexCAN controller area network (CAN) module

? Three universal asynchronous/synchronous

receiver/transmitters (UARTs)

? Inter-integrated circuit (I2C?) bus controller

? Queued serial peripheral interface (QSPI) module

? Eight-channel 10- or 12-bit fast analog-to-digital converter

(ADC)

? Four channel direct memory access (DMA) controller

? Four 32-bit input capture/output compare timers with

DMA support (DTIM)

? Four-channel general-purpose timer (GPT) capable of

input capture/output compare, pulse width modulation

(PWM) and pulse accumulation

? Eight/Four-channel 8/16-bit pulse width modulation timers

(two adjacent 8-bit PWMs can be concatenated to form a

single 16-bit timer)

MCF52235CAL60                          Features

? External reset input

? Power-on reset (POR)

? Watchdog timer

? Phase locked-loop (PLL) loss of lock

? PLL loss of clock

? Software