MK20DN512VLL10 Description

MK20DN512VLL10 have some Errata ID such as CJTAG. On exceedingly rare occasions, the IEEE 1149.7 (Compact JTAG interface) may reset itself when switching from Standard Protocol to Advanced Protocol. In this scenario, the CJTAG will reset all internal registers and go back to the Standard Protocol mode. In order to keep the CJTAG Test Access Port (TAP) controller in the Run-Test-Idle state until the Check Packet is finished, the IEEE 1149.7 module (CJTAG) internally gates the TCK clock to the TAP controller while processing a Check Packet. The CJTAG TAP controller could experience a bug that would lead it to switch states rather than stay in the Run-Test-Idle state during the transition from the Preamble element to the first Body element of Check Packet processing.

MK20DN512VLL10 Features

• Bit Size: 32

• Voltage - Supply (Vcc/Vdd): 1.71V~3.6V

• Core Processor: ARM? Cortex?-M4

• RAM Size: 128K x 8

• Program Memory Size: 512KB 512K x 8

• Supply Current-Max: 77mA

MK20DN512VLL10 Applications

• Power Management

• Consumer Electronics

• Portable Devices

• Industrial