MPC561MZP56  Features

High-performance microprocessor

— Single clock-cycle execution for many instructions

Five independent execution units and two register files

— Independent LSU for load and store operations

— BPU featuring static branch prediction

— A 32-bit integer unit (IU)

— 32 general-purpose registers (GPRs) for integer operands

— 32 floating-point registers (FPRs) for single- or double-precision operands

Facilities for enhanced system performance

— Atomic memory references

In-system testability and debugging features

High instruction and data throughput

— Condition register (CR) look-ahead operations performed by BPU

— Branch-folding capability during execution (zero-cycle branch execution time)

— Programmable static branch prediction on unresolved conditional branches

— A pre-fetch queue that can hold up to four instructions, providing the look-ahead capability

— Interlocked pipelines with feed-forwarding that control data dependencies in hardware

Class code compression model support

— Efficient use of internal Flash (MPC564) and external Flash (MPC562/MPC564) by increasing

code density up to 100%