MPC8377CVRALG Description

This chip incorporates the e300c4s core, which includes 32 KB of L1 instruction and data caches, and on-chip memory management units (MMUs). The device offers two enhanced three-speed 10, 100, and 1000 Mbps Ethernet interfaces, a DDR1/DDR2 SDRAM memory controller, a flexible, 32-bit local bus controller, a 32-bit PCI controller, an optional dedicated security engine, a USB 2.0 dual-role controller, a programmable interrupt controller, dual I2C controllers, a 4-channel DMA controller, an enhanced secured digital host controller, and a general-purpose I/O port. This figure shows the block diagram of the chip.

MPC8377CVRALG Features

e300c4s core built on Power Architecture? technology with 32 KB instruction cache and 32 KB

data cache, a floating point unit, and two integer units

DDR1/DDR2 memory controller supporting a 32/64-bit interface

Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MT/s operation

32-bit local bus interface running up to 133-MT/s

USB 2.0 (full/high speed) support

Power management controller for low-power consumption

High degree of software compatibility with previous-generation PowerQUICC processor-based

designs for backward compatibility and easier software migration

Optional security engine provides acceleration for control and data plane security protocols