P5020NXN7VNB Description

The dual-core P5020 and single-core P5010 processors deliver 64-bit processing, based on the e5500 core built on Power Architecture? technology. With frequencies scalable to 2.0 GHz, large caches, and high per-cycle efficiency, these products target control planes and computer applications that require high single-threaded performance. The P5 platform leverages architectural features pioneered in the P4 platform, including the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, and data path acceleration architecture (DPAA) for offloading packet handling tasks from the core, and the CoreNet? switch fabric that eliminates internal bottlenecks. This enables architectural compatibility from the P5 platform to the P4 platform as well as to the P3 platform.

P5020NXN7VNB Features

Core Complex

Single or dual 64-bit e5500 cores offered at 2.0 GHz

Three-level cache-hierarchy: 32 KB I/D L1; 512 KB private L2 per core; 2 MB shared L3

Up to 2.0 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)

Three levels of instruction: user, supervisor, hypervisor

Hybrid 32-bit mode to support legacy software and transition to 64-bit architecture

2.0 MB configures as a dual 1 MB platform cache

Networking Elements

SerDes

18 lanes at up to 5 Gbps

Supports SGMII, Serial RapidIO?, XAUI, PCI Express? (PCIe) rev1.1/2.0, SATA

Ethernet interfaces

10 Gbps Ethernet MAC

Five 1 Gbps Ethernet MACs

Accelerators and memory control

Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support

Up to 1300MT/s

Frame manager for packet handling

Queue manager for policing, scheduling, and workload distribution

Security block for crypto algorithm acceleration

RAID5/6 for parity calculations in storage applications

RapidIO message manager for type 9 and 11 messaging

Pattern matching engine for regular expression searches

P5020NXN7VNB  Applications

Ethernet Switch