SPC5517EBMLQ66

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Manufacturer part number:SPC5517EBMLQ66

Manufacturer:NXP USA Inc.

Description:1.5MB 1.5M x 8 FLASH e200z0, e200z1 32-Bit Dual-Core Microcontroller MPC55xx Qorivva Series SPC5517 5V 144-LQFP

Case Package:SOT-23

Datasheet:SPC5517EBMLQ66 Datasheet

RoHs Status:non-compliant

Name	Value
Type	Parameter
Factory Lead Time	12 Weeks
Mounting Type	Surface Mount
Package / Case	144-LQFP
Surface Mount	YES
Operating Temperature	-40°C~125°C TA
Packaging	Tray
Series	MPC55xx Qorivva
Published	2004
JESD-609 Code	e3
Part Status	Active
Moisture Sensitivity Level (MSL)	3 (168 Hours)
Number of Terminations	144
ECCN Code	3A991.A.2
Terminal Finish	Matte Tin (Sn)
HTS Code	8542.31.00.01
Terminal Position	QUAD
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	5V
Terminal Pitch	0.5mm
Time@Peak Reflow Temperature-Max (s)	40
Base Part Number	SPC5517
JESD-30 Code	S-PQFP-G144
Qualification Status	Not Qualified
Supply Voltage-Max (Vsup)	5.25V
Power Supplies	5V
Supply Voltage-Min (Vsup)	4.5V
Oscillator Type	Internal
Number of I/O	111
Speed	66MHz
RAM Size	80K x 8
Voltage - Supply (Vcc/Vdd)	4.5V~5.25V
uPs/uCs/Peripheral ICs Type	MICROCONTROLLER
Core Processor	e200z0, e200z1
Peripherals	DMA, POR, PWM, WDT
Clock Frequency	40MHz
Program Memory Type	FLASH
Core Size	32-Bit Dual-Core
Program Memory Size	1.5MB 1.5M x 8
Connectivity	CANbus, EBI/EMI, I2C, SCI, SPI
Bit Size	32
Data Converter	A/D 40x12b
Has ADC	YES
DMA Channels	YES
PWM Channels	NO
DAC Channels	NO
Address Bus Width	23
ROM (words)	196608
Screening Level	AEC-Q100
External Data Bus Width	23
Length	20mm
Height Seated (Max)	1.6mm
Width	20mm
RoHS Status	ROHS3 Compliant

The SPC5517EBMLQ66 is a 32-Bit Power Architecture? Microcontroller for Body Electronics from MPC5510 Family.

Up to 1.5 MB of on-chip flash with a flash control unit (FCU)
Up to 80 KB on-chip SRAM
Memory protection unit (MPU) with up to 16 region descriptors and 32-byte region granularity
Interrupt controller (INTC) capable of handling selectable-priority interrupt sources
Frequency modulated Phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to peripherals, flash, or RAM from multiple bus masters
One 16-channel enhanced direct memory access controller (eDMA)
Boot assist module (BAM) supports internal flash programming via a serial link (CAN or SCI)
Timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse-width modulation functions (eMIOS200)
One 12-bit analogue-to-digital converter (ADC)
Up to four serial peripheral interfaces (DSPI) modules
Up to eight serial communication interface (eSCI) modules
Up to six enhanced full CAN (FlexCAN) modules with configurable buffers