SPC5676RDK3MVY1  Description

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC5676R. The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however, for production silicon, these specifications will be met. Finalized specifications will be published after complete characterization and device

qualifications have been completed.

SPC5676RDK3MVY1  Features

Two identical dual issues, 32-bit CPU core complexes

(e200z7), each with

– Power Architecture embedded specification compliance

– Instruction set enhancement allowing variable length

encoding (VLE), optional encoding of mixed 16-bit and

32-bit instructions, for code size footprint reduction

– Signal processing extension (SPE) instruction support

for digital signal processing (DSP)

– Single-precision floating point operations (FPU)

– 16 KB I-Cache and 16 KB D-Cache

– Hardware cache coherency between cores

16 Hardware semaphores

3 channel CRC module

6MB on-chip flash

– Supports reading during the program and erase operations, and

multiple blocks allowing EEPROM emulation

384KB on-chip general-purpose SRAM including 48KB of

standby RAM

Two multi-channel direct memory access controllers

(eDMA)

– 64 channels per eDMA

Dual-core Interrupt controller (INTC)

Phase-locked loop with FM modulation (FMPLL)

Crossbar switch architecture for concurrent access to

peripherals, flash, or RAM from multiple bus masters

External Bus Interface (EBI) for calibration and

application development

System integration unit (SIU) with error correction status

module (ECSM)

Four protected port output pins (PPO)

Boot assist module (BAM) supports serial bootload via

CAN or SCI

Three second-generation enhanced time processor units

(eTPU2)