ST72T213G1M6

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Manufacturer part number:ST72T213G1M6

Manufacturer:STMicroelectronics

Description:8-bit Microprocessor 5V SOIC

Case Package:SOT-23

Datasheet:ST72T213G1M6 Datasheet

RoHs Status:non-compliant

Name	Value
Type	Parameter
Package / Case	SOIC
Surface Mount	YES
JESD-609 Code	e0
Number of Terminations	28
Terminal Finish	TIN LEAD
Max Operating Temperature	85°C
Min Operating Temperature	-40°C
Subcategory	Microcontrollers
Technology	CMOS
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	NOT SPECIFIED
Supply Voltage	5V
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED
Pin Count	28
JESD-30 Code	R-PDSO-G28
Qualification Status	Not Qualified
Temperature Grade	INDUSTRIAL
Interface	SPI
Max Supply Voltage	5.5V
Min Supply Voltage	3.5V
Memory Size	4kB
Number of I/O	22
RAM Size	256B
Memory Type	EPROM, OTP
uPs/uCs/Peripheral ICs Type	MICROCONTROLLER
Supply Current-Max	20mA
Bit Size	8
Frequency (Max)	8MHz
Has ADC	YES
DMA Channels	NO
Data Bus Width	8b
PWM Channels	YES
DAC Channels	NO
Number of Timers/Counters	1
ROM (words)	4096
CPU Family	ST72
Number of Programmable I/O	22
RAM (bytes)	256
ROM Programmability	OTPROM
Height Seated (Max)	2.65mm
RoHS Status	RoHS Compliant

The ST72T213G1M6 is a real-time development tool for the ST7 MCU Family that consists of various hardware and software components.

A common Hardware Development System mainframe supports the entire ST7 family of MCUs, in conjunction with the appropriate
ST7xxx-DBE Dedicated Board Emulator.
Real-time source-level emulation allows viewing and breakpoint settings on high-level source code rather than on disassembled target code for optimum user-friendliness.
64 KBytes of user-modifiable and configurable emulation RAM, allows memory mapping of all ST7 family devices as well as modelling
hypothetical memory configurations.
Unlimited breakpoints may be set for any opcode fetch or any address access, and conditions may be defined for the generation of 2 external synchronization signals.
1K by 32-bit wide trace memory for Logic Analyzer allows complex and sequential events to be defined on any combination of address and data, as well as 3 internal and 5 external logic signals.