STD65N55F3 datasheet pdf and Transistors - FETs, MOSFETs - Single product details from STMicroelectronics stock available on our website
SOT-23
STD65N55F3 Datasheet
non-compliant
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Specifications
Name
Value
Type
Parameter
Lifecycle Status
ACTIVE (Last Updated: 8 months ago)
Contact Plating
Tin
Mount
Surface Mount
Mounting Type
Surface Mount
Package / Case
TO-252-3, DPak (2 Leads + Tab), SC-63
Number of Pins
3
Transistor Element Material
SILICON
Operating Temperature
-55°C~175°C TJ
Packaging
Tape & Reel (TR)
Series
STripFET™
JESD-609 Code
e3
Part Status
Active
Moisture Sensitivity Level (MSL)
1 (Unlimited)
Number of Terminations
2
ECCN Code
EAR99
Subcategory
FET General Purpose Power
Technology
MOSFET (Metal Oxide)
Terminal Form
GULL WING
Peak Reflow Temperature (Cel)
260
[email protected] Reflow Temperature-Max (s)
30
Base Part Number
STD65N
Pin Count
3
JESD-30 Code
R-PSSO-G2
Number of Elements
1
Power Dissipation-Max
110W Tc
Element Configuration
Single
Operating Mode
ENHANCEMENT MODE
Power Dissipation
110W
Case Connection
DRAIN
Turn On Delay Time
20 ns
FET Type
N-Channel
Transistor Application
SWITCHING
Rds On (Max) @ Id, Vgs
8.5m Ω @ 32A, 10V
Vgs(th) (Max) @ Id
4V @ 250μA
Input Capacitance (Ciss) (Max) @ Vds
2200pF @ 25V
Current - Continuous Drain (Id) @ 25°C
80A Tc
Gate Charge (Qg) (Max) @ Vgs
45nC @ 10V
Rise Time
50ns
Drive Voltage (Max Rds On,Min Rds On)
10V
Vgs (Max)
±20V
Fall Time (Typ)
11.5 ns
Turn-Off Delay Time
35 ns
Continuous Drain Current (ID)
32A
Threshold Voltage
4V
Gate to Source Voltage (Vgs)
20V
Drain Current-Max (Abs) (ID)
80A
Drain-source On Resistance-Max
0.0085Ohm
Drain to Source Breakdown Voltage
55V
Height
2.4mm
Length
6.6mm
Width
6.2mm
Radiation Hardening
No
REACH SVHC
No SVHC
RoHS Status
ROHS3 Compliant
Lead Free
Lead Free
Pricing & Ordering
Quantity
Unit Price
Ext. Price
2,500
$1.31990
$2.6398
5,000
$1.27656
$6.3828
STD65N55F3 Product Details
STD65N55F3 Description
The STD65N55F3 is a STripFET? N-channel enhancement-mode Power MOSFET designed with the latest refinement of the unique Single Feature Size? strip-based process. The process decreased the critical alignment steps, offering remarkable manufacturing reproducibility. The outcome is a transistor with extremely high packing density for low ON-resistance, rugged avalanche characteristics, and low gate charge.