CANbus, I2C, IrDA, LINbus, MMC, SPI, UART/USART, USB OTG
Supply Current-Max
81mA
Bit Size
32
Data Converter
A/D 16x12b; D/A 2x12b
Watchdog Timer
Yes
Data Bus Width
32b
Number of Timers/Counters
14
ROM (words)
524288
Core Architecture
ARM
CPU Family
CORTEX-M3
REACH SVHC
No SVHC
Radiation Hardening
No
RoHS Status
ROHS3 Compliant
Lead Free
Lead Free
Pricing & Ordering
Quantity
Unit Price
Ext. Price
1
$11.04000
$11.04
90
$9.51156
$856.0404
180
$8.25883
$1486.5894
540
$7.19169
$3883.5126
STM32F215VET6 Product Details
STM32F215VET6 Description
The high-performance ARM?Cortex?-M3 32-bit RISC core of the STM32F215VET6 operates at a frequency of up to 120 MHz. The STM32F215VET6 includes a wide range of upgraded I/Os and peripherals connected to two APB buses, three AHB buses, and a 32-bit multi-AHB bus matrix, as well as high-speed embedded memories (Flash memory up to 1 Mbyte, up to 128 Kbytes of system SRAM, up to 4 Kbytes of backup SRAM). The STM32F215VET6 also includes an adaptive real-time memory accelerator (ART AcceleratorTM), which enables executing programs from Flash memory with performance comparable to zero wait states at a CPU frequency of up to 120 MHz. The CoreMark benchmark has been used to verify this performance.
The STM32F215VET6 provides two general-purpose 32-bit timers, three 12-bit ADCs, two DACs, a low-power RTC, and twelve general-purpose 16-bit timers, including two PWM timers for motor control. a real random number generator (RNG). It also has both conventional and cutting-edge communication interfaces. An SDIO, an improved flexible static memory control (FSMC) interface (for products provided in packages of 100 pins and more), a cryptographic acceleration cell, and a camera interface for CMOS sensors are examples of new sophisticated peripherals. Standard peripherals are also included with the devices.
STM32F215VET6 Features
96-bit unique ID
CRC calculation unit
2 × 12-bit D/A converters
General-purpose DMA: 16-stream controller with centralized FIFOs and burst support
Debug mode: Serial wire debug (SWD), JTAG, and Cortex-M3 Embedded Trace Macrocell?
3 × 12-bit, 0.5 μs ADCs with up to 24 channels and up to 6 MSPS in triple interleaved mode