CANbus, I2C, IrDA, LINbus, MMC, SPI, UART/USART, USB OTG
Supply Current-Max
81mA
Bit Size
32
Data Converter
A/D 24x12b; D/A 2x12b
Watchdog Timer
Yes
Has ADC
YES
DMA Channels
YES
Data Bus Width
32b
Number of Timers/Counters
14
Core Architecture
ARM
Number of UART Channels
2
Number of ADC Channels
24
Number of PWM Channels
6
Number of I2C Channels
3
Height
1.45mm
Length
20.2mm
Width
20.2mm
REACH SVHC
No SVHC
Radiation Hardening
No
RoHS Status
ROHS3 Compliant
Lead Free
Lead Free
Pricing & Ordering
Quantity
Unit Price
Ext. Price
1
$10.61000
$10.61
60
$9.34283
$560.5698
120
$8.23183
$987.8196
540
$7.32280
$3954.312
1,020
$6.71676
$6.71676
STM32F215ZET6 Product Details
STM32F215ZET6 Description
The high-performance ARM?Cortex?-M3 32-bit RISC core that runs at a frequency of up to 120 MHz is the foundation of the STM32F21x family. The family has a wide range of upgraded I/Os and peripherals connected to two APB buses, three AHB buses, and a 32-bit multi-AHB bus matrix, along with high-speed embedded memories (Flash memory up to 1 Mbyte, up to 128 Kbytes of system SRAM, up to 4 Kbytes of backup SRAM).
The devices additionally include an adaptive real-time memory accelerator (ART AcceleratorTM), which enables program execution from Flash memory with performance similar to zero wait states at CPU frequencies up to 120 MHz. The CoreMark? benchmark has been used to certify this performance. STM32F215ZET6 features two general-purpose 32-bit timers, three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers, and two PWM timers for motor control. a real random number generator (RNG). They also have both conventional and cutting-edge communication interfaces. An SDIO, an improved flexible static memory control (FSMC) interface (for products provided in packages of 100 pins and more), a cryptographic acceleration cell, and a camera interface for CMOS sensors are examples of new sophisticated peripherals. Standard peripherals are also included with the devices.
STM32F215ZET6 Features
2 × 12-bit D/A converters
3 × 12-bit, 0.5 μs ADCs with up to 24 channels and up to 6 MSPS in triple interleaved mode
General-purpose DMA: 16-stream controller with centralized FIFOs and burst support
Debug mode: Serial wire debug (SWD), JTAG, and Cortex?-M3 Embedded Trace Macrocell?
Core: ARM? 32-bit Cortex?-M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator?) allowing 0-wait state execution performance from Flash memory, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1)