STM32F765VIH6 Description
Based on the powerful 32-bit RISC Arm? Cortex?-M7 CPU, the STM32F765VIH6 can operate up to 216 MHz. The floating point unit (FPU) of the Cortex?-M7 core of the STM32F765VIH6 supports Arm? double-precision and single-precision data-processing instructions and data formats. The application security is improved by adding a memory protection unit (MPU) and a full range of DSP instructions in the STM32F765VIH6.
STM32F765VIH6 Features
Includes ST state-of-the-art patented technology
Core: Arm? 32-bit Cortex?-M7 CPU with DPFPU, ART Accelerator, and L1-cache: 16 Kbytes I/D cache, allowing 0-wait state execution from embedded Flash and external memories, up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions.
Memories
Up to 2 Mbytes of Flash memory organized into two banks allowing read-while-write
SRAM: 512 Kbytes (including 128 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for essential real-time routines) + 4 Kbytes of backup SRAM
Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
Dual mode Quad-SPI
Graphics
Chrom-ART Accelerator (DMA2D), graphical hardware accelerator enabling enhanced graphical user interface
Hardware JPEG codec
LCD-TFT controller supporting up to XGA resolution
MIPI? DSI host controller supporting up to 720p 30 Hz resolution
Clock, reset, and supply management
1.7 V to 3.6 V application supply and I/Os
POR, PDR, PVD, and BOR
Dedicated USB power
4-to-26 MHz crystal oscillator
Internal 16 MHz factory-trimmed RC (1% accuracy)
32 kHz oscillator for RTC with calibration
Internal 32 kHz RC with calibration
Low-power
Sleep, Stop and Standby modes
VBAT supply for RTC, 32×32 bit backup registers + 4 Kbytes backup SRAM
STM32F765VIH6 Applications
Motor control systems
Display units
SMPS and Power Regulation systems
Digital data processing
Industrial control systems
Analog signal measuring and manipulations
Embedded systems like coffee machines, vending machines
Peripheral Interface system