STM32G473VBT6            Description

  The STM32G473xB/XC/XE device is based on a high-performance ARM Cortex - M4 32-bit RISC core. They operate at frequencies as high as 170 MHz. The Cortex-M4 kernel uses a single-precision floating-point unit (FPU) and supports all ARM single-precision data processing instructions and all data types. It also implements a complete set of DSP (Digital signal processing) instructions and a memory protection unit (MPU) that enhances application security. These devices embed high-speed memory (512K-byte flash memory and 128K-byte SRAM), a flexible external memory controller (FSMC) for static memory, four SPI flash memory interfaces, and various enhanced APB O and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. These devices also embed several protection mechanisms for embedded flash memory and SRAM: read protection, write protection, secure storage area, and proprietary code read protection. These devices embed peripherals that allow mathematical / arithmetic function acceleration (CORDIC for trigonometric functions and FMAC units for filter functions). They provide 5 fast 12-bit ADC (4 MSPS), 7 comparators, 6 operational amplifiers, 7 DAC channels (3 external and 4 internal), 1 internal reference buffer, 1 low power RTC, 2 32-bit universal timers, 3 16-bit PWM timers specifically for motor control, 7 generic 16-bit timers and 1 16-bit low power timer.

STM32G473VBT6                   Features

Includes ST state-of-the-art patented

technology

? Core: Arm? 32-bit Cortex?-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator) allowing 0-wait-state execution

from Flash memory, frequency up to 170 MHz

with 213 DMIPS, MPU, DSP instructions

? Operating conditions:

– VDD, VDDA voltage range:

1.71 V to 3.6 V

? Mathematical hardware accelerators

– CORDIC for trigonometric functions

acceleration

– FMAC: filter mathematical accelerator

? Memories

– 512 Kbytes of Flash memory with ECC

support, two banks read-while-write,

proprietary code readout protection

(PCROP), securable memory area, 1 Kbyte

OTP

– 96 Kbytes of SRAM, with hardware parity

check implemented on the first 32 Kbytes

– Routine booster: 32 Kbytes of SRAM on

instruction and data bus, with hardware

parity check (CCM SRAM)

– External memory interface for static

memories FSMC supporting SRAM,

PSRAM, NOR and NAND memories

– Quad-SPI memory interface

? Reset and supply management

– Power-on/power-down reset

(POR/PDR/BOR)

– Programmable voltage detector (PVD)

– Low-power modes: sleep, stop, standby

and shutdown

– VBAT supply for RTC and backup registers

STM32G473VBT6                  Applications

static memory