STPCI2HEYC Description

The STPC Consumer integrates a standard 5th generation x86 core, a DRAM controller, a graphics subsystem, a video pipeline, and support logic including PCI, ISA, and IDE controllers to provide a single Consumer orientated PC compatible subsystem on a single device. The device is based on a tightly coupled Unified Memory Architecture (UMA), sharing the same memory array between the CPU main memory and the graphics and video frame buffers. Extra facilities are implemented to handle video streams. Features include smooth scaling and color space conversion of the video input stream and mixing with graphics data. The chip also includes a built-in digital TV encoder and anti-flicker filters that allow stable, high-quality display on standard PAL or NTSC television sets without additional components. The STPC Consumer is packaged in a 388 Plastic Ball Grid Array (PBGA).

STPCI2HEYC Features

POWERFUL X86 PROCESSOR

64-BIT BUS ARCHITECTURE

64-BIT DRAM CONTROLLER

SVGA GRAPHICS CONTROLLER

UMA ARCHITECTURE

VIDEO SCALER

DIGITAL PAL/NTSC ENCODER

VIDEO INPUT PORT

CRT CONTROLLER

135MHz RAMDAC

3 LINE FLICKER FILTER

SCAN CONVERTER

PCI MASTER / SLAVE / ARBITER CTRL

ISA MASTER/SLAVE INTERFACE

IDE CONTROLLER

DMA CONTROLLER

INTERRUPT CONTROLLER

TIMER / COUNTERS

POWER MANAGEMENT