M3358BZCZA100 Description

  AM3358BZCZA100 microprocessors are based on ARM Cortex-A8 processors and are enhanced with image, graphics processing, peripherals, and industrial interface options such as EtherCAT and PROFIBUS. These devices support Advanced operating system (HLOS). Processors SDK Linux and TI-RTOS are available free of charge from TI. The AM335x microprocessor includes the subsystems shown in the functional block diagram, and each subsystem is briefly described: the microprocessor unit subsystem is based on the ARM Cortex-A8 processor, and the PowerVR SGX graphics accelerator subsystem provides 3D graphics acceleration to support display and game effects. PRU-ICSS is separated from the ARM kernel and allows independent operation and timing for greater efficiency and flexibility. PRU-ICSS supports other peripheral interfaces and real-time protocols, such as EtherCAT, PROFINET, Ethernet / IP, PROFIBUS, Ethernet Powerlink, SERCOS, etc. In addition, PRU-ICSS 's programmability and access to pins, events, and all system-on-a-chip (SoC) resources provide flexibility for fast real-time response, specialized data processing operations, customized peripheral interfaces, and offloading tasks from other processor cores of SoC.

AM3358BZCZA100 Features

? Up to 1-GHz Sitara? ARM? Cortex?

-A8 32?Bit

RISC Processor

– NEON? SIMD Coprocessor

– 32KB of L1 Instruction and 32KB of Data Cache

With Single-Error Detection (Parity)

– 256KB of L2 Cache With Error Correcting Code

(ECC)

– 176KB of On-Chip Boot ROM

– 64KB of Dedicated RAM

– Emulation and Debug - JTAG

– Interrupt Controller (up to 128 Interrupt

Requests)

? On-Chip Memory (Shared L3 RAM)

– 64KB of General-Purpose On-Chip Memory

Controller (OCMC) RAM

– Accessible to All Masters

– Supports Retention for Fast Wakeup

? External Memory Interfaces (EMIF)

– mDDR(LPDDR), DDR2, DDR3, DDR3L

Controller:

– mDDR: 200-MHz Clock (400-MHz Data Rate)

– DDR2: 266-MHz Clock (532-MHz Data Rate)

– DDR3: 400-MHz Clock (800-MHz Data Rate)

– DDR3L: 400-MHz Clock (800-MHz Data

Rate)

– 16-Bit Data Bus

– 1GB of Total Addressable Space

– Supports One x16 or Two x8 Memory Device

Configurations

– General-Purpose Memory Controller (GPMC)

– Flexible 8-Bit and 16-Bit Asynchronous

Memory Interface With up to Seven Chip

Selects (NAND, NOR, Muxed-NOR, SRAM)

– Uses BCH Code to Support 4-, 8-, or 16-Bit

ECC

– Uses Hamming Code to Support 1-Bit ECC

– Error Locator Module (ELM)

– Used in Conjunction With the GPMC to

Locate Addresses of Data Errors from

Syndrome Polynomials Generated Using a

BCH Algorithm

– Supports 4-, 8-, and 16-Bit per 512-Byte

Block Error Location Based on BCH

AM3358BZCZA100  Applications

? Connected Vending Machines

? Weighing Scales

? Educational Consoles

? Advanced Toys

? Gaming Peripherals

? Home and Industrial Automation

? Consumer Medical Appliances

? Printers

? Smart Toll Systems