3V~18V 16MHz 6 Bit D-Type Flip Flop DUAL CD40174 16 Pins 4μA 4000B Series 16-TSSOP (0.173, 4.40mm Width)
SOT-23
CD40174BPWRE4 Datasheet
non-compliant
In-Stock: 0 items
Specifications
Name
Value
Type
Parameter
Mount
Surface Mount
Mounting Type
Surface Mount
Package / Case
16-TSSOP (0.173, 4.40mm Width)
Number of Pins
16
Weight
61.887009mg
Operating Temperature
-55°C~125°C TA
Packaging
Tape & Reel (TR)
Series
4000B
Part Status
Obsolete
Moisture Sensitivity Level (MSL)
1 (Unlimited)
Number of Terminations
16
Type
D-Type
Subcategory
FF/Latches
Packing Method
TAPE AND REEL
Technology
CMOS
Voltage - Supply
3V~18V
Terminal Position
DUAL
Terminal Form
GULL WING
Peak Reflow Temperature (Cel)
NOT SPECIFIED
Supply Voltage
5V
[email protected] Reflow Temperature-Max (s)
NOT SPECIFIED
Base Part Number
CD40174
Function
Master Reset
Qualification Status
Not Qualified
Output Type
Non-Inverted
Number of Elements
1
Polarity
Non-Inverting
Supply Voltage-Min (Vsup)
3V
Load Capacitance
50pF
Number of Bits
6
Clock Frequency
16MHz
Propagation Delay
300 ns
Turn On Delay Time
50 ns
Current - Quiescent (Iq)
4μA
Current - Output High, Low
6.8mA 6.8mA
Max Propagation Delay @ V, Max CL
100ns @ 15V, 50pF
Trigger Type
Positive Edge
Input Capacitance
5pF
Number of Input Lines
6
fmax-Min
8 MHz
Clock Edge Trigger Type
Positive Edge
Max [email protected]
3500000Hz
Length
5mm
Width
4.4mm
RoHS Status
ROHS3 Compliant
Lead Free
Lead Free
CD40174BPWRE4 Product Details
CD40174BPWRE4 Overview
16-TSSOP (0.173, 4.40mm Width)is the packaging method. Package Tape & Reel (TR)embeds it. In the configuration, Non-Invertedis used as the output. It is configured with a trigger that uses Positive Edge. It is mounted in the way of Surface Mount. Powered by a 3V~18Vvolt supply, it operates as follows. Temperature is set to -55°C~125°C TA. This D latch has the type D-Type. FPGAs belonging to the 4000Bseries contain this type of chip. Its output frequency should not exceed 16MHz Hz. The list contains 1 elements. This process consumes 4μA quiescents. In 16terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. Members of the CD40174family make up this object. Power is supplied from a voltage of 5V volts. Its input capacitance is 5pF farads. There is an electronic part that is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 16. Its clock edge trigger type is Positive Edge. The part is included in FF/Latches. There are 6bits in its design. The supply voltage (Vsup) should be maintained above 3V for normal operation. Considering its reliability, this T flip flop is well suited for TAPE AND REEL. It is reported that there are 6 input lines.