LP2998QMR/NOPB Description

The LP2998QMR/NOPB linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR- SDRAM and DDR2 memory. The LP2998QMR/NOPB also supports DDR3 and DDR3L VTT bus termination with Vopo min of 1.35 V. The LP2998QMR/NOPB contains a high-speed operational amplifier to provide an excellent response to load transients. The output stage prevents shoot-through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998QMR/NOPB also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

LP2998QMR/NOPB Features

AEC-Q100 Test Guidance with the following results (SO PowerPAD-8):

 -Device HBM ESD Classification Level H1C

 -Junction Temperature Range - 40°C to 125°C

1.35 V Minimum Vppa

Source and Sink Current

Low Output Voltage Offset

No External Resistors Required

Linear Topology

Suspend to Ram (STR) Functionality

Low External Component Count

Thermal Shutdown

LP2998QMR/NOPB Applications

DDR1, DDR2, DDR3, and DDR3L Termination Voltage

Automotive Infotainment

FPGA.

Industrial/Medical PC

SSTL-18, SSTL-2, and SSTL-3 Termination

HSTL Termination