PGA112AIDGSR Description The PGA112 and PGA113 devices (binary and scopegains) offer two analog inputs, a three-pin SPIinterface, and software shutdown in a 10-pin, VSSOPpackage. The PGA116 and PGA117 (binary andscope gains) offer 10 analog inputs, a SPI interfacewith daisy-chain capability, and hardwareandsoftware shutdown in a 20-pin TSSOP package. All versions provide internal calibration channels forsystem-level calibration. The channels are tied toGND，0.9 VcAL，0.1 VcAL, and VREF， respectively.VcaL, an external voltage connected to Channel 0, isused as the system calibration reference. Binarygains are: 1, 2, 4, 8, 16, 32, 64, and 128, scope gainsare: 1, 2, 5, 10, 20, 50, 100, and 200. PGA112AIDGSR Features Rail-to-Rail Input and Output Offset: 25 μV (Typical), 100 μV (Maximum) Zerø Drift: 0.35 μV/°C (Typical), 1.2 μV/°C(Maximum) Low Noise: 12 nV/√Hz Input Offset Current: ±5 nA Maximum (25°C) Gain Error: 0.1% Maximum (G ≤ 32), 0.3% Maximum (G > 32) Gain Switching Time: 200 ns Four Internal Calibration Channels PGA112AIDGSR Applications Remote e-Meter Reading Automatic Gain Control Portable Data Acquisition PC-Based Signal Acquisition Systems Test and Measurement Programmable Logic Controllers Battery-Powered Instruments Handheld Test Equipment