SN65DSI83ZQERDescription

The SN65DSI83ZQER is a Single-channel MIPI® DSI to single-link LVDS bridge & Flatlink™ integrated circuit.

SN65DSI83ZQER Features

• Implements MIPI® D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00

• Single channel DSI receiver configurable for 1, 2, 3, or 4 D-PHY data lanes per channel operating up to 1 Gbps/lane

• Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats

• FlatLink™ output for single-link LVDS

• Supports single-channel DSI to single-link LVDS operating mode

• LVDS Output Clock Range of 25 MHz to 154 MHz

• LVDS pixel clock may be sourced from a freerunning continuous D-PHY clock or external reference clock (REFCLK)

• 1.8-V main VCC power supply

• Low power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support

• LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing

• ESD rating ±2 kV (HBM)

• Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)

• Temperature range: –40°C to 85°C

SN65DSI83ZQER Applications

• PC & notebooks

• Tablets

• Connected peripherals & printers