SN65DSI86IPAPQ1 Description

The SN65DSI86IPAPQ1 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps. The SN65DSI86IPAPQ1 is well suited for WQXGA at 60 frames per second and 3D graphics at 4K and true HD (1920 x 1080) resolutions at an equivalent of 120 fps with up to 24 bpp. Partial line buffering accommodates the data stream mismatch between the DSI and DisplayPort interfaces.

SN65DSI86IPAPQ1 Features

MIPI Front-End Configurable for Single-Channel or Dual-Channel DSI Configuration

Supports Dual-Channel DSI Odd, Even, and Left, Right Operating Modes

1.2-V Main VCC Power Supply and 1.8-V Supply for Digital l/Os

Low-Power Features Include Panel Refresh and MIPI Ultralow Power State (ULPS) Support

DisplayPort Lane Polarity and Assignment Configurable.

Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz, and 38.4-MHz Frequencies Through External Reference Clock (REFCLK)

ESD Rating +2 kV (HBM)

Packaged in 64-Terminal HTQFP (PAP)

Temperature Range: - 40°C to +85°C

SN65DSI86IPAPQ1 Applications

Tablet PCs

Notebook PCs

Netbooks

Mobile Internet Devices

Automotive Infotainment