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SN74HC273ANSR

SN74HC273ANSR

SN74HC273ANSR

Texas Instruments

2V~6V 72MHz D-Type Flip Flop 74HC273 8μA 74HC Series 20-SOIC (0.209, 5.30mm Width)

SOT-23

SN74HC273ANSR Datasheet

non-compliant

In-Stock: 0 items
Specifications
Name Value
Type Parameter
Factory Lead Time 6 Weeks
Mounting Type Surface Mount
Package / Case 20-SOIC (0.209, 5.30mm Width)
Operating Temperature -40°C~85°C TA
Packaging Tape & Reel (TR)
Series 74HC
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Type D-Type
Voltage - Supply 2V~6V
Base Part Number 74HC273
Function Master Reset
Output Type Non-Inverted
Number of Elements 1
Polarity Non-Inverting
Clock Frequency 72MHz
Current - Quiescent (Iq) 8μA
Current - Output High, Low 5.2mA 5.2mA
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 25ns @ 6V, 50pF
Trigger Type Positive Edge
Input Capacitance 3pF
RoHS Status ROHS3 Compliant
Pricing & Ordering
Quantity Unit Price Ext. Price
SN74HC273ANSR Product Details

SN74HC273ANSR Overview


The flip flop is packaged in 20-SOIC (0.209, 5.30mm Width). A package named Tape & Reel (TR)includes it. Currently, the output is configured to use Non-Inverted. It is configured with a trigger that uses Positive Edge. Surface Mountis in the way of this electric part. The JK flip flop operates with an input voltage of 2V~6V volts. It is at -40°C~85°C TAdegrees Celsius that the system is operating. It is an electronic flip flop with the type D-Type. In terms of FPGAs, it belongs to the 74HC series. A frequency of 72MHzshould be the maximum output frequency. D latch consists of 1 elements. This process consumes 8μA quiescents. You can search similar parts based on 74HC273. This T flip flop has a capacitance of 3pF farads at the input.

SN74HC273ANSR Features


Tape & Reel (TR) package
74HC series

SN74HC273ANSR Applications


There are a lot of Texas Instruments SN74HC273ANSR Flip Flops applications.

  • ESD protection
  • Safety Clamp
  • Communications
  • Convert a momentary switch to a toggle switch
  • Power down protection
  • Individual Asynchronous Resets
  • High Performance Logic for test systems
  • Latch
  • CMOS Process
  • Computing

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