TPS51200AQDRCTQ1 Description

The TPS51200AQDRCTQ1 is a sink and source double-data-rate (DDR) termination regulator that is optimized for low input voltage, low-cost and low-noise systems with limited space.

The TPS51200AQDRCTQ1 regulator has a quick transient response and requires only a 20-F output capacitance. All power needs for DDR, DDR2, DDR3, and Low Power DDR3 and DDR4 VTT bus termination are supported by the device, as well as a remote sensing feature.

TPS51200AQDRCTQ1 Features

• AEC-Q100 Qualified for Automotive Applications:

• Device Temperature Grade 1:

• –40°C ≤ TA ≤ 125°C

• Device HBM ESD Classification Level 2

• Device CDM ESD Classification Level C4B

• Extended Reliability Testing

• Input Voltage: Supports 2.5-V Rail and 3.3-V Rail

• VLDOIN Voltage Range: 1.1 V to 3.5 V

• Sink and Source Termination Regulator Includes Droop Compensation

• Requires Minimum Output Capacitance of 20-μF (typically 3 × 10-μF MLCCs) for Memory Termination Applications (DDR)

• PGOOD to Monitor Output Regulation

• EN Input

• REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider

• Remote Sensing (VOSNS)

• ±10-mA Buffered Reference (REFOUT)

• Built-in Soft-Start, UVLO, and OCL

• Thermal Shutdown

• Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3 and DDR4 VTT Applications

• VSON-10 Package With Exposed Thermal Pad

TPS51200AQDRCTQ1 Applications

• Memory Termination Regulator for DDR, DDR2, DDR3, and Low Power DDR3/DDR4

• Notebook

• Desktop

•  Server

• Telecom and Datacom

• GSM Base Station

• LCDTV and PDP-TV

• Copier and Printer, Set-Top Box