UCC3837DTRG4 datasheet pdf and PMIC - Voltage Regulators - Linear Regulator Controllers product details from Texas Instruments stock available on our website
SOT-23
UCC3837DTRG4 Datasheet
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Specifications
Name
Value
Type
Parameter
Package / Case
8-SOIC (0.154, 3.90mm Width)
Surface Mount
YES
Number of Pins
8
Weight
69.994973mg
Operating Temperature
0°C~70°C
Packaging
Tape & Reel (TR)
JESD-609 Code
e4
Pbfree Code
no
Part Status
Obsolete
Moisture Sensitivity Level (MSL)
2 (1 Year)
Number of Terminations
8
Type
Positive Adjustable
Terminal Finish
Nickel/Palladium/Gold (Ni/Pd/Au)
Subcategory
Other Analog ICs
Technology
BICMOS
Terminal Position
DUAL
Terminal Form
GULL WING
Peak Reflow Temperature (Cel)
260
Number of Functions
1
Supply Voltage
5V
Base Part Number
UCC3837
Pin Count
8
Number of Outputs
1
Output Voltage
9V
Output Type
Adjustable
Max Output Current
2.5mA
Operating Supply Current
1.2mA
Voltage - Input
2.2V~12V
Output Current
1.5mA
Quiescent Current
1.2mA
Max Output Voltage
9V
Min Input Voltage
3V
Max Input Voltage
12V
Min Output Voltage
1.5V
Length
4.9mm
Width
3.9mm
Radiation Hardening
No
RoHS Status
ROHS3 Compliant
Lead Free
Contains Lead
UCC3837DTRG4 Product Details
UCC3837DTRG4 Description
All the features needed for an extremely low dropout linear regulator that uses an external N-channel MOSFET as the pass transistor are included in the UCC3837 Linear Regulator Controller. An effective linear solution for custom processor voltages, bus termination voltages, and other logic level voltages below 3V is provided by the device since it can operate from input voltages as low as 3V and can offer high current levels. When driving an external N-MOSFET, the onboard charge pump generates a gate drive voltage that is ideal for low dropout voltage and good efficiency. The extensive adaptability of this IC enables the user to optimize the setting of the output voltage and current limit for applications outside of or within the typical limits of a 3-terminal linear regulator.
This 8-pin controller IC uses a duty ratio current limiting approach that limits the average power dissipation of the pass transistor under fault conditions while providing peak transient loading capacity. For further information, see the Application Section.