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XCV150-6FGG456C

XCV150-6FGG456C

XCV150-6FGG456C

Xilinx

2.5V V FPGAs FBGA 1mm mm 456

SOT-23

XCV150-6FGG456C Datasheet PDF

non-compliant

Technical Specifications

Parameter NameValue
TypeParameter
Package / Case FBGA
Surface MountYES
JESD-609 Code e1
Pbfree Code yes
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 456
ECCN Code EAR99
Terminal Finish Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
Max Operating Temperature85°C
Min Operating Temperature 0°C
HTS Code8542.39.00.01
Technology CMOS
Terminal Position BOTTOM
Terminal FormBALL
Peak Reflow Temperature (Cel) 250
Supply Voltage 2.5V
Terminal Pitch1mm
Time@Peak Reflow Temperature-Max (s) 30
Pin Count456
Operating Supply Voltage2.5V
Temperature GradeOTHER
RAM Size 6kB
Clock Frequency 333MHz
Programmable Logic TypeFIELD PROGRAMMABLE GATE ARRAY
Speed Grade 6
Number of CLBs 864
Length 23mm
Width 23mm
Radiation HardeningNo
RoHS StatusRoHS Compliant
In-Stock:4582 items

XCV150-6FGG456C Product Details

XCV150-6FGG456C Overview


Fpga chips is supplied in the FBGA package. This kind of FPGA is composed of FIELD PROGRAMMABLE GATE ARRAY. Fpga chips is powered from a supply voltage of 2.5V. Fpga chips is designed wFpga chipsh 456 terminations. The RAM si6kBe of this FPGA module reaches 6kB to ensure normal operation of the program. When operating with the supply voltage of 2.5V, designers can fully make use of its flexibility. The maximal operating temperature of this module reaches 85°C. The operating temperature should be higher than 0°C. Fpga semiconductor is equipped wfpga semiconductorh 456 pin count. Typically, fpga semiconductor uses a crystal oscillating at 333MHz . 864 CLBs are basic modules used for its architecture.

XCV150-6FGG456C Features


85°C gates


XCV150-6FGG456C Applications


There are a lot of Xilinx
XCV150-6FGG456C FPGAs applications.


  • Digital signal processing
  • Bioinformatics
  • Device controllers
  • Software-defined radio
  • Random logic
  • ASIC prototyping
  • Medical imaging
  • Computer hardware emulation
  • Integrating multiple SPLDs
  • Voice recognition

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