XC5VSX95T-2FFG1136C

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Manufacturer part number:XC5VSX95T-2FFG1136C

Manufacturer:Xilinx Inc.

Description:3.4mm mm FPGAs Virtex?-5 SXT Series 1136-BBGA, FCBGA 1mm mm

Case Package:SOT-23

Datasheet:XC5VSX95T-2FFG1136C Datasheet

RoHs Status:non-compliant

Name	Value
Type	Parameter
Factory Lead Time	10 Weeks
Mounting Type	Surface Mount
Package / Case	1136-BBGA, FCBGA
Surface Mount	YES
Operating Temperature	0°C~85°C TJ
Packaging	Tray
Published	1999
Series	Virtex®-5 SXT
JESD-609 Code	e1
Pbfree Code	yes
Part Status	Active
Moisture Sensitivity Level (MSL)	4 (72 Hours)
ECCN Code	3A991.D
Terminal Finish	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
HTS Code	8542.39.00.01
Subcategory	Field Programmable Gate Arrays
Technology	CMOS
Voltage - Supply	0.95V~1.05V
Terminal Position	BOTTOM
Terminal Form	BALL
Peak Reflow Temperature (Cel)	245
Supply Voltage	1V
Terminal Pitch	1mm
Reach Compliance Code	not_compliant
[email protected] Reflow Temperature-Max (s)	30
Base Part Number	XC5VSX95T
JESD-30 Code	S-PBGA-B1136
Number of Outputs	640
Qualification Status	Not Qualified
Power Supplies	12.5V
Number of I/O	640
Clock Frequency	1265MHz
Number of Inputs	640
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Number of Logic Elements/Cells	94208
Total RAM Bits	8994816
Number of LABs/CLBs	7360
Height Seated (Max)	3.4mm
Length	35mm
Width	35mm
RoHS Status	ROHS3 Compliant

Quantity	Unit Price	Ext. Price
1	$4,205.37000	$4

The XC5VSX95T-2FFG1136C is from the Virtex-5 family using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture.

Five platforms LX, LXT, SXT, TXT, and FXT
Cross-platform compatibility
Most advanced, high-performance, optimal-utilization, FPGA fabric
Powerful clock management tile (CMT) clocking
36-Kbit block RAM/FIFOs
High-performance parallel SelectIO technology
Advanced DSP48E slices
Flexible configuration options
System Monitoring capability on all devices
On average, one to two-speed grade improvement over Virtex-4 devices
Cascadable 32-bit variable shift registers or 64-bit distributed memory capability
Superior routing architecture with enhanced diagonal routing supports block-to-block connectivity with minimal hops