2.54mm mm 1GB B FPGAs Kintex?-7 Series 676-BBGA, FCBGA 1mm mm 676
SOT-23
XC7K325T-2FBG676C Datasheet
non-compliant
In-Stock: 0 items
Specifications
Name
Value
Type
Parameter
Factory Lead Time
11 Weeks
Contact Plating
Copper, Silver, Tin
Mounting Type
Surface Mount
Package / Case
676-BBGA, FCBGA
Surface Mount
YES
Number of Pins
676
Operating Temperature
0°C~85°C TJ
Packaging
Tray
Published
2010
Series
Kintex®-7
JESD-609 Code
e1
Pbfree Code
yes
Part Status
Active
Moisture Sensitivity Level (MSL)
4 (72 Hours)
Number of Terminations
676
ECCN Code
3A991.D
Terminal Finish
Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
HTS Code
8542.39.00.01
Subcategory
Field Programmable Gate Arrays
Technology
CMOS
Voltage - Supply
0.97V~1.03V
Terminal Position
BOTTOM
Terminal Form
BALL
Peak Reflow Temperature (Cel)
NOT SPECIFIED
Supply Voltage
1V
Terminal Pitch
1mm
[email protected] Reflow Temperature-Max (s)
NOT SPECIFIED
Base Part Number
XC7K325T
Pin Count
676
Number of Outputs
400
Qualification Status
Not Qualified
Power Supplies
11.83.3V
Memory Size
1GB
Number of I/O
400
RAM Size
2MB
Memory Type
DDR3
Clock Frequency
1818MHz
Programmable Logic Type
FIELD PROGRAMMABLE GATE ARRAY
Number of Logic Elements/Cells
326080
Total RAM Bits
16404480
Number of LABs/CLBs
25475
Speed Grade
-2
Number of Registers
407600
Combinatorial Delay of a CLB-Max
0.61 ns
Height Seated (Max)
2.54mm
Length
27mm
Width
27mm
RoHS Status
ROHS3 Compliant
Pricing & Ordering
Quantity
Unit Price
Ext. Price
1
$1,120.60000
$1
XC7K325T-2FBG676C Product Details
XC7K325T-2FBG676C Description
The XC7K325T-2FBG676C is from Xilinx® 7 series FPGAs.
XC7K325T-2FBG676C Features
Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.
36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.
High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.
High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to max. rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.
A user-configurable analogue interface (XADC), incorporating dual 12-bit 1MSPS analogue-to-digital converters with on-chip thermal and supply sensors.
DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering.
Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.
Quickly deploy embedded processing with MicroBlaze™ processor.
Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.
Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction