74LV273PW,118 Overview

The package is in the form of 20-TSSOP (0.173, 4.40mm Width). D flip flop is included in the Tape & Reel (TR)package. Non-Invertedis the output configured for it. There is a trigger configured with Positive Edge. The electronic part is mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 1V~5.5V. The operating temperature is -40°C~125°C TA. A flip flop of this type is classified as a D-Type. It belongs to the 74LVseries of FPGAs. Its output frequency should not exceed 100MHz Hz. D latch consists of 1 elements. This process consumes 160μA quiescents. The 74LV273 family contains it. This JK flip flop has a 3.5pFfarad input capacitance. This electronic part is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 20. Its clock edge trigger type is Positive Edge. It is designed with a number of bits of 8. The superior flexibility of this circuit is achieved by using 1 circuits. High efficiency requires the supply voltage to be maintained at 3.3V. With a current output of 25mA , it offers maximum design flexibility. There are 8 output lines in this JK flip flop. As of now, there are 8input lines. -12mA is set as the high level output current. Low level output current is set to 12mA. It is recommended that the operating temperature be below 125°C. The operating temperature should be higher than -40°C. A minimum supply voltage of 1V is required for these RS flip flops to operate. It is capable of supporting a maximum supply voltage of 5.5V. 100MHzis the maximum frequency that can be achieved.

74LV273PW,118 Features

Tape & Reel (TR) package
74LV series
20 pins
8 Bits

74LV273PW,118 Applications

There are a lot of Nexperia USA Inc. 74LV273PW,118 Flip Flops applications.

• Buffer registers
• Power down protection
• Set-reset capability
• Convert a momentary switch to a toggle switch
• Parallel data storage
• Individual Asynchronous Resets
• CMOS Process
• Reduced system switching noise
• Shift registers
• Synchronous counter