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74AC377SJX

74AC377SJX

74AC377SJX

ON Semiconductor

2V~6V 175MHz D-Type Flip Flop 74AC377 40μA 74AC Series 20-SOIC (0.209, 5.30mm Width)

SOT-23

74AC377SJX Datasheet

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In-Stock: 0 items
Specifications
Name Value
Type Parameter
Mounting Type Surface Mount
Package / Case 20-SOIC (0.209, 5.30mm Width)
Supplier Device Package 20-SOP
Operating Temperature -40°C~85°C TA
Packaging Tape & Reel (TR)
Series 74AC
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Type D-Type
Voltage - Supply 2V~6V
Base Part Number 74AC377
Function Standard
Output Type Non-Inverted
Number of Elements 1
Clock Frequency 175MHz
Current - Quiescent (Iq) 40μA
Current - Output High, Low 24mA 24mA
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 9ns @ 5V, 50pF
Trigger Type Positive Edge
Input Capacitance 4.5pF
Pricing & Ordering
Quantity Unit Price Ext. Price
1 $3.685224 $3.685224
10 $3.476627 $34.76627
100 $3.279836 $327.9836
500 $3.094185 $1547.0925
1000 $2.919042 $2919.042
74AC377SJX Product Details

74AC377SJX Overview


The flip flop is packaged in 20-SOIC (0.209, 5.30mm Width). Package Tape & Reel (TR)embeds it. Non-Invertedis the output configured for it. The trigger it is configured with uses Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A 2V~6Vsupply voltage is required for it to operate. A temperature of -40°C~85°C TAis used in the operation. D-Typedescribes this flip flop. It is a type of FPGA belonging to the 74AC series. A frequency of 175MHzshould be the maximum output frequency. A total of 1elements are contained within it. As a result, it consumes 40μA quiescent current. JK flip flop belongs to 74AC377 family. The input capacitance of this T flip flop is 4.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded.

74AC377SJX Features


Tape & Reel (TR) package
74AC series

74AC377SJX Applications


There are a lot of ON Semiconductor 74AC377SJX Flip Flops applications.

  • QML qualified product
  • Parallel data storage
  • Bus hold
  • Event Detectors
  • Reduced system switching noise
  • Common Clocks
  • Guaranteed simultaneous switching noise level
  • Single Down Count-Control Line
  • Set-reset capability
  • Modulo – n – counter

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