FDMS3600S datasheet pdf and Transistors - FETs, MOSFETs - Arrays product details from ON Semiconductor stock available on our website
SOT-23
FDMS3600S Datasheet
non-compliant
In-Stock: 0 items
Specifications
Name
Value
Type
Parameter
Factory Lead Time
13 Weeks
Lifecycle Status
ACTIVE (Last Updated: 2 days ago)
Mount
Surface Mount
Number of Pins
8
Weight
171mg
Packaging
Tape & Reel (TR)
JESD-609 Code
e3
Pbfree Code
yes
Part Status
Active
Moisture Sensitivity Level (MSL)
1 (Unlimited)
Number of Terminations
7
ECCN Code
EAR99
Terminal Finish
Tin (Sn)
Max Operating Temperature
150°C
Min Operating Temperature
-55°C
Subcategory
FET General Purpose Power
Max Power Dissipation
1W
Terminal Position
QUAD
JESD-30 Code
R-PQFP-N7
Number of Elements
2
Element Configuration
Dual
Operating Mode
ENHANCEMENT MODE
Power Dissipation
2.5W
Case Connection
DRAIN SOURCE
Transistor Application
SWITCHING
Rise Time
5.3ns
Drain to Source Voltage (Vdss)
25V
Polarity/Channel Type
N-CHANNEL
Fall Time (Typ)
3.9 ns
Turn-Off Delay Time
38 ns
Continuous Drain Current (ID)
30A
Gate to Source Voltage (Vgs)
20V
Drain Current-Max (Abs) (ID)
15A
Drain to Source Breakdown Voltage
25V
Input Capacitance
1.68nF
FET Technology
METAL-OXIDE SEMICONDUCTOR
Drain to Source Resistance
1.6mOhm
Rds On Max
5.6 mΩ
Nominal Vgs
1.8 V
Feedback Cap-Max (Crss)
90 pF
Height
1.05mm
Length
5mm
Width
6mm
Radiation Hardening
No
REACH SVHC
No SVHC
RoHS Status
ROHS3 Compliant
Pricing & Ordering
Quantity
Unit Price
Ext. Price
3,000
$1.15830
$3.4749
6,000
$1.11540
$6.6924
FDMS3600S Product Details
FDMS3600S Description
In a twin PQFN packaging, this device has two specialized N-Channel MOSFETs. To make synchronous buck converter placement and routing simple, the switch node has been internally connected. To offer maximum power efficiency, the control MOSFET (Q1) and synchronous SyncFETTM (Q2) have been created.
FDMS3600S Features
Maximum RDS(on) at VGS = 10 V, ID = 30 A is 1.6 m.
At VGS = 4.5 V, ID = 25 A, the maximum RDS(on) is 2.4 m.
Reduced rise/fall periods due to reduced inductance packing reduce switching losses.
Optimal designing for lower circuit inductance and less switch node ringing is made possible by MOSFET integration.