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FDV302P

FDV302P

FDV302P

ON Semiconductor

FDV302P datasheet pdf and Transistors - FETs, MOSFETs - Single product details from ON Semiconductor stock available on our website

SOT-23

FDV302P Datasheet

non-compliant

In-Stock: 0 items
Specifications
Name Value
Type Parameter
Factory Lead Time 10 Weeks
Lifecycle Status ACTIVE (Last Updated: 16 hours ago)
Contact Plating Tin
Mount Surface Mount
Mounting Type Surface Mount
Package / Case TO-236-3, SC-59, SOT-23-3
Number of Pins 3
Weight 30mg
Transistor Element Material SILICON
Operating Temperature -55°C~150°C TJ
Packaging Tape & Reel (TR)
Published 1997
JESD-609 Code e3
Pbfree Code yes
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 3
ECCN Code EAR99
Resistance 13Ohm
Additional Feature LOGIC LEVEL COMPATIBLE
Subcategory Other Transistors
Voltage - Rated DC -25V
Technology MOSFET (Metal Oxide)
Terminal Position DUAL
Terminal Form GULL WING
Current Rating -120mA
Number of Elements 1
Number of Channels 1
Power Dissipation-Max 350mW Ta
Element Configuration Single
Operating Mode ENHANCEMENT MODE
Power Dissipation 350mW
Turn On Delay Time 5 ns
FET Type P-Channel
Transistor Application SWITCHING
Rds On (Max) @ Id, Vgs 10 Ω @ 200mA, 4.5V
Vgs(th) (Max) @ Id 1.5V @ 250μA
Input Capacitance (Ciss) (Max) @ Vds 11pF @ 10V
Current - Continuous Drain (Id) @ 25°C 120mA Ta
Gate Charge (Qg) (Max) @ Vgs 0.31nC @ 4.5V
Rise Time 8ns
Drain to Source Voltage (Vdss) 25V
Drive Voltage (Max Rds On,Min Rds On) 2.7V 4.5V
Vgs (Max) ±8V
Fall Time (Typ) 8 ns
Turn-Off Delay Time 9 ns
Continuous Drain Current (ID) 120mA
Threshold Voltage -1V
Gate to Source Voltage (Vgs) -8V
Drain to Source Breakdown Voltage -25V
Dual Supply Voltage -25V
Max Junction Temperature (Tj) 150°C
Nominal Vgs -1 V
Height 1.11mm
Length 2.92mm
Width 1.3mm
Radiation Hardening No
REACH SVHC No SVHC
RoHS Status ROHS3 Compliant
Lead Free Lead Free
FDV302P Product Details

FDV302P Description


Our exclusive high cell density DMOS technology is used to make the FDV302P transistor. This extremely dense technique is specifically designed to reduce on-state resistance. This device was created specifically to replace digital transistors in low-voltage applications. This single P-channel FET can replace numerous digital transistors with various bias resistors, such as the DTCx and DCDx series, because bias resistors are not required.



FDV302P Features


  • Gate drive needs are very minimal, allowing direct operation in 3V circuits. VGS(th) < 1.5V.

  • For ESD toughness, use a Gate-Source Zener.

  • Human Body Model >6kV

  • SOT-23 surface mount package is a compact industry standard.

  • One DMOS FET can replace multiple PNP digital transistors (DTCx and DCDx).



FDV302P Applications


FDV302P is intended for general use and can be used in a variety of situations.


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