74AUP2G79GN,115 Overview

It is embeded in 8-XFDFN case. It is contained within the Tape & Reel (TR)package. In the configuration, Non-Invertedis used as the output. Positive Edgeis the trigger it is configured with. Surface Mountis positioned in the way of this electronic part. The JK flip flop operates at 0.8V~3.6Vvolts. A temperature of -40°C~125°C TAis used in the operation. This electronic flip flop is of type D-Type. In FPGA terms, D flip flop is a type of 74AUPseries FPGA. You should not exceed 309MHzin the output frequency of the device. A total of 2elements are contained within it. Despite external influences, it consumes 500nAof quiescent current. There have been 8 terminations. The 74AUP2G79family includes it. It is powered from a supply voltage of 1.1V. JK flip flop input capacitance is 0.6pF farads. In terms of electronic devices, this device belongs to the AUP/ULP/Vfamily of devices. There is an electronic component mounted in the way of Surface Mount. As you can see from the design, it has pins with 8. This device exhibits a clock edge trigger type of Positive Edge. There is a 3.6Vmaximum supply voltage (Vsup).

74AUP2G79GN,115 Features

Tape & Reel (TR) package
74AUP series
8 pins

74AUP2G79GN,115 Applications

There are a lot of Nexperia USA Inc. 74AUP2G79GN,115 Flip Flops applications.

• Digital electronics systems
• Circuit Design
• Safety Clamp
• Shift Registers
• EMI reduction circuitry
• QML qualified product
• Differential Individual
• Guaranteed simultaneous switching noise level
• Test & Measurement
• Registers