FDG6321C Description

On Semiconductor's patented, high cell density DMOS technology is used to create these dual N & P-Channel logic level enhancement mode field effect transistors. Onstate resistance is specifically reduced by this very high density method. This device was created specifically as a low voltage substitute for small signal MOSFETS and bipolar digital transistors. This dual digital FET can replace numerous distinct digital transistors with various bias resistor values because bias resistors are not necessary.

FDG6321C Features

• SC70-very 6's compact packaging shape.

• low-level gate drive specifications that permit direct

• VGS(th) 1.5 V operating in 3 V circuits.

• For ESD robustness (>6kV human body model), use a gate-source zener.

FDG6321C Applications

Switching applications