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FDPC5018SG

  • FDPC5018SG
  • FDPC5018SG

FDPC5018SG

FDPC5018SG

ON Semiconductor

FDPC5018SG datasheet pdf and Transistors - FETs, MOSFETs - Arrays product details from ON Semiconductor stock available on our website

SOT-23

FDPC5018SG Datasheet

non-compliant

In-Stock: 0 items
Specifications
Name Value
Type Parameter
Factory Lead Time 23 Weeks
Lifecycle Status ACTIVE (Last Updated: 3 days ago)
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 8-PowerWDFN
Number of Pins 8
Weight 207.7333mg
Transistor Element Material SILICON
Operating Temperature -55°C~150°C TJ
Packaging Tape & Reel (TR)
Series PowerTrench®
JESD-609 Code e3
Pbfree Code yes
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 8
ECCN Code EAR99
Terminal Finish Tin (Sn)
Max Power Dissipation 1.1W
Terminal Form NO LEAD
Peak Reflow Temperature (Cel) 260
Reach Compliance Code not_compliant
[email protected] Reflow Temperature-Max (s) NOT SPECIFIED
Number of Elements 2
Configuration SERIES CONNECTED, CENTER TAP, 2 ELEMENTS WITH BUILT-IN DIODE
Operating Mode ENHANCEMENT MODE
Power - Max 1W 1.1W
FET Type 2 N-Channel (Dual) Asymmetrical
Transistor Application SWITCHING
Rds On (Max) @ Id, Vgs 5m Ω @ 17A, 10V
Vgs(th) (Max) @ Id 3V @ 250μA
Input Capacitance (Ciss) (Max) @ Vds 1715pF @ 15V
Current - Continuous Drain (Id) @ 25°C 17A 32A
Gate Charge (Qg) (Max) @ Vgs 24nC @ 10V
Drain to Source Voltage (Vdss) 30V
Continuous Drain Current (ID) 32A
Drain Current-Max (Abs) (ID) 17A
Drain-source On Resistance-Max 0.005Ohm
DS Breakdown Voltage-Min 30V
FET Technology METAL-OXIDE SEMICONDUCTOR
FET Feature Standard
Feedback Cap-Max (Crss) 60 pF
RoHS Status ROHS3 Compliant
Pricing & Ordering
Quantity Unit Price Ext. Price
3,000 $0.75735 $2.27205
6,000 $0.72930 $4.3758
FDPC5018SG Product Details

FDPC5018SG          Description


  The device includes two specialized N-channel MOSFET in the dual package. The switch nodes are connected internally for easy placement and wiring of synchronous step-down converters. The control of MOSFET (Q1) and synchronous FET (Q2) is designed to provide optimal power efficiency.


FDPC5018SG            Features

 

Q1 N-Channel

Max. RDS(on) = 5.0 m|? at VGS = 10 V, ID = 17 A

Max. RDS(on) = 6.5 m|? at VGS = 10 V, ID = 17 A

Q2 N-Channel

Max. RDS(on) = 1.6 m|? at VGS = 10 V, ID = 32 A

Max. RDS(on) = 2.0 m|? at VGS = 4.5 V, ID = 28 A

Low Inductance Packaging Shortens Rise/Fall Times, Resulting in Lower Switching Losses

MOSFET Integration Enables Optimum Layout for Lower Circuit Inductance and Reduced Switch Node Ringing

RoHS Compliant


FDPC5018SG                 Applications

Computing

Communications

General Purpose Point of Load

 

 

 





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