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FDPC5030SG

  • FDPC5030SG
  • FDPC5030SG

FDPC5030SG

FDPC5030SG

ON Semiconductor

FDPC5030SG datasheet pdf and Transistors - FETs, MOSFETs - Arrays product details from ON Semiconductor stock available on our website

SOT-23

FDPC5030SG Datasheet

non-compliant

In-Stock: 0 items
Specifications
Name Value
Type Parameter
Factory Lead Time 23 Weeks
Lifecycle Status ACTIVE (Last Updated: 3 days ago)
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 8-PowerWDFN
Number of Pins 8
Weight 207.7333mg
Operating Temperature -55°C~150°C TJ
Packaging Tape & Reel (TR)
Published 2017
Series PowerTrench®
JESD-609 Code e3
Pbfree Code yes
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
ECCN Code EAR99
Terminal Finish Tin (Sn)
Max Power Dissipation 1.1W
Peak Reflow Temperature (Cel) 260
Reach Compliance Code not_compliant
[email protected] Reflow Temperature-Max (s) NOT SPECIFIED
Power - Max 1W 1.1W
FET Type 2 N-Channel (Dual) Asymmetrical
Rds On (Max) @ Id, Vgs 5m Ω @ 17A, 10V
Vgs(th) (Max) @ Id 3V @ 250μA
Input Capacitance (Ciss) (Max) @ Vds 1715pF @ 15V
Current - Continuous Drain (Id) @ 25°C 17A 25A
Gate Charge (Qg) (Max) @ Vgs 24nC @ 10V
Drain to Source Voltage (Vdss) 30V
Continuous Drain Current (ID) 25A
FET Feature Standard
RoHS Status ROHS3 Compliant
Pricing & Ordering
Quantity Unit Price Ext. Price
3,000 $0.69670 $2.0901
6,000 $0.66186 $3.97116
15,000 $0.63698 $9.5547
FDPC5030SG Product Details

FDPC5030SG         Description

 

  The device includes two specialized N-channel MOSFET in the dual package. The switch node is connected internally to facilitate the placement and wiring of the synchronous step-down converter. The control of MOSFET (Q1) and synchronous FET (Q2) is designed to provide optimal power efficiency.

 


FDPC5030SG      Features

 

Q1 N-Channel

Max. RDS(on) = 5.0 m|? at VGS = 10 V, ID = 17 A

Max. RDS(on) = 6.5 m|? at VGS = 4.5 V, ID = 14 A

Q2 N-Channel

Max. RDS(on) = 2.4 m|? at VGS = 10 V, ID = 25 A

Max. RDS(on) = 3.0 m|? at VGS = 4.5 V, ID = 22 A

Low Inductance Packaging Shortens Rise/Fall Times, Resulting in Lower Switching Losses

MOSFET Integration Enables Optimum Layout for Lower Circuit Inductance and Reduced Switch Node Ringing

RoHS Compliant


FDPC5030SG             Applications


Computing

Communications

General Purpose Point of Load

 





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