MC100EP35DR2G Overview

The package is in the form of 8-SOIC (0.154, 3.90mm Width). You can find it in the Tape & Reel (TR)package. This output is configured with Differential. Positive Edgeis the trigger it is configured with. There is an electric part mounted in the way of Surface Mount. A voltage of -3V~-5.5Vis used as the supply voltage. A temperature of -40°C~85°C TAis considered to be the operating temperature. This D latch has the type JK Type. JK flip flop is a part of the 100EPseries of FPGAs. Its output frequency should not exceed 3GHz Hz. A total of 1 elements are present. It consumes 50mA of quiescent current without being affected by external factors. The number of terminations is 8. The power supply voltage is 3.3V. It is designed with a number of bits of 2. As soon as 5.5Vis reached, Vsup reaches its maximum value. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 3V. Additionally, you may refer to the D latch's additional NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V.

MC100EP35DR2G Features

Tape & Reel (TR) package
100EP series
2 Bits

MC100EP35DR2G Applications

There are a lot of Rochester Electronics, LLC MC100EP35DR2G Flip Flops applications.

• Divide a clock signal by 2 or 4
• Matched Rise and Fall
• Safety Clamp
• Latch
• Bounce elimination switch
• Count Modes
• Registers
• ESD protection
• Counters
• QML qualified product