STE110NS20FD datasheet pdf and Transistors - FETs, MOSFETs - Single product details from STMicroelectronics stock available on our website
SOT-23
STE110NS20FD Datasheet
non-compliant
In-Stock: 0 items
Specifications
Name
Value
Type
Parameter
Mount
Chassis Mount, Screw
Mounting Type
Chassis Mount
Package / Case
ISOTOP
Number of Pins
4
Transistor Element Material
SILICON
Operating Temperature
150°C TJ
Packaging
Tube
Series
MESH OVERLAY™
Part Status
Obsolete
Moisture Sensitivity Level (MSL)
1 (Unlimited)
Number of Terminations
4
ECCN Code
EAR99
Terminal Finish
Nickel (Ni)
Additional Feature
AVALANCHE RATED
Subcategory
FET General Purpose Power
Voltage - Rated DC
200V
Technology
MOSFET (Metal Oxide)
Terminal Position
UPPER
Terminal Form
UNSPECIFIED
Peak Reflow Temperature (Cel)
NOT SPECIFIED
Reach Compliance Code
not_compliant
Current Rating
110A
[email protected] Reflow Temperature-Max (s)
NOT SPECIFIED
Base Part Number
STE1
Pin Count
4
Qualification Status
Not Qualified
Number of Elements
1
Configuration
SINGLE WITH BUILT-IN DIODE
Power Dissipation-Max
500W Tc
Operating Mode
ENHANCEMENT MODE
Power Dissipation
500W
Case Connection
ISOLATED
FET Type
N-Channel
Transistor Application
SWITCHING
Rds On (Max) @ Id, Vgs
24m Ω @ 50A, 10V
Vgs(th) (Max) @ Id
4V @ 250μA
Input Capacitance (Ciss) (Max) @ Vds
7900pF @ 25V
Current - Continuous Drain (Id) @ 25°C
110A Tc
Gate Charge (Qg) (Max) @ Vgs
504nC @ 10V
Rise Time
130ns
Drive Voltage (Max Rds On,Min Rds On)
10V
Vgs (Max)
±20V
Fall Time (Typ)
140 ns
Turn-Off Delay Time
245 ns
Continuous Drain Current (ID)
110A
Gate to Source Voltage (Vgs)
20V
Drain to Source Breakdown Voltage
200V
Avalanche Energy Rating (Eas)
750 mJ
RoHS Status
ROHS3 Compliant
Pricing & Ordering
Quantity
Unit Price
Ext. Price
100
$29.00000
$2900
STE110NS20FD Product Details
STE110NS20FD Description
STMicroelectronics has developed a cutting-edge series of Power MOSFETs with exceptional performances using the most recent high voltage MESH OVERLAYTM technology. With the help of the company's exclusive edge termination structure and the newly-patentable STrip layout, the lowest RDS(ON) per area, remarkable avalanche and dv/dt capabilities, and unmatched gate charge and switching characteristics may be achieved.