CSD13201W10 datasheet pdf and Transistors - FETs, MOSFETs - Single product details from Texas Instruments stock available on our website
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CSD13201W10 Datasheet
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Specifications
Name
Value
Type
Parameter
Factory Lead Time
6 Weeks
Lifecycle Status
ACTIVE (Last Updated: 5 days ago)
Contact Plating
Copper, Silver, Tin
Mount
Surface Mount
Mounting Type
Surface Mount
Package / Case
4-UFBGA, DSBGA
Number of Pins
4
Transistor Element Material
SILICON
Operating Temperature
-55°C~150°C TJ
Packaging
Tape & Reel (TR)
Series
NexFET™
JESD-609 Code
e1
Pbfree Code
yes
Part Status
Active
Moisture Sensitivity Level (MSL)
1 (Unlimited)
Number of Terminations
4
ECCN Code
EAR99
Terminal Finish
Tin/Silver/Copper (Sn/Ag/Cu)
Technology
MOSFET (Metal Oxide)
Terminal Position
BOTTOM
Terminal Form
BALL
Peak Reflow Temperature (Cel)
260
[email protected] Reflow Temperature-Max (s)
NOT SPECIFIED
Base Part Number
CSD13201
Number of Elements
1
Number of Channels
1
Power Dissipation-Max
1.2W Ta
Element Configuration
Single
Operating Mode
ENHANCEMENT MODE
Power Dissipation
1.2W
Turn On Delay Time
3.9 ns
FET Type
N-Channel
Transistor Application
SWITCHING
Rds On (Max) @ Id, Vgs
34m Ω @ 1A, 4.5V
Vgs(th) (Max) @ Id
1.1V @ 250μA
Input Capacitance (Ciss) (Max) @ Vds
462pF @ 6V
Current - Continuous Drain (Id) @ 25°C
1.6A Ta
Gate Charge (Qg) (Max) @ Vgs
2.9nC @ 4.5V
Rise Time
5.9ns
Drive Voltage (Max Rds On,Min Rds On)
1.8V 4.5V
Vgs (Max)
±8V
Fall Time (Typ)
9.7 ns
Turn-Off Delay Time
14.4 ns
Continuous Drain Current (ID)
1.6A
Gate to Source Voltage (Vgs)
8V
Drain-source On Resistance-Max
0.053Ohm
Drain to Source Breakdown Voltage
12V
Pulsed Drain Current-Max (IDM)
20.2A
Feedback Cap-Max (Crss)
22.6 pF
Height
625μm
Length
0m
Width
0m
Thickness
650μm
RoHS Status
ROHS3 Compliant
Lead Free
Lead Free
Pricing & Ordering
Quantity
Unit Price
Ext. Price
3,000
$0.13860
$0.4158
6,000
$0.13020
$0.7812
15,000
$0.12180
$1.827
CSD13201W10 Product Details
CSD13201W10 Description
CSD13201W10 emerges as a member of the family of N-channel NexFET? power MOSFET. It is able to provide ultra-low Qg and Qgd, as well as a gate-source voltage clamp. It is specifically designed to offer low on-state resistance and low gate charge in a low profile while ensuring good thermal characteristics.