74AUP1G175GW,125 Overview

In the form of 6-TSSOP, SC-88, SOT-363, it has been packaged. A package named Tape & Reel (TR)includes it. Currently, the output is configured to use Non-Inverted. It is configured with a trigger that uses Positive Edge. This electronic part is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 0.8V~3.6V volts. Temperature is set to -40°C~125°C TA. This D latch has the type D-Type. JK flip flop belongs to the 74AUPseries of FPGAs. Its output frequency should not exceed 300MHz. In total, there are 1 elements. As a result, it consumes 500nA quiescent current and is not affected by external forces. D latch belongs to the 74AUP1G175 family. A 0.8pFfarad input capacitance is provided by this T flip flop. There is an electronic part mounted in the way of Surface Mount. 6pins are included in its design. This device's clock edge trigger type is Positive Edge. There are 1bits in this flip flop. Despite its superior flexibility, it relies on 1 circuits to achieve it. There are 1 output lines in this JK flip flop. It is reported that there are 1 input lines. It consumes 500nA of quiescent current without being affected by external factors. A high level output current of -4mAis set. A 4mAvalue is set for low-level output current. Ideally, the operating temperature should be below 125°C. It is recommended that the operating temperature is higher than -40°C. It is powered by 800mV as its minimum supply voltage. The maximum supply voltage supported by the flip flop is 3.6V. We are able to achieve a frequency of 50MHz.

74AUP1G175GW,125 Features

Tape & Reel (TR) package
74AUP series
6 pins
1 Bits

74AUP1G175GW,125 Applications

There are a lot of Nexperia USA Inc. 74AUP1G175GW,125 Flip Flops applications.

• Buffered Clock
• Data transfer
• Test & Measurement
• Event Detectors
• Control circuits
• Memory
• Data Synchronizers
• Cold spare funcion
• Automotive
• Storage Registers