74AUP1G79GS,132 Overview

It is packaged in the way of 6-XFDFN. You can find it in the Tape & Reel (TR)package. In the configuration, Non-Invertedis used as the output. JK flip flop uses Positive Edgeas the trigger. Surface Mountis positioned in the way of this electronic part. The supply voltage is set to 0.8V~3.6V. In the operating environment, the temperature is -40°C~125°C TA. D-Typeis the type of this D latch. In FPGA terms, D flip flop is a type of 74AUPseries FPGA. A frequency of 309MHzshould be the maximum output frequency. In total, there are 1 elements. A total of 6 terminations have been made. The 74AUP1G79family includes it. A voltage of 1.1V is used as the power supply for this D latch. Its input capacitance is 0.8pFfarads. A device of this type belongs to the family of AUP/ULP/V. There is an electronic component mounted in the way of Surface Mount. Basically, it is designed with a set of 6 pins. In this device, the clock edge trigger type is Positive Edge. There are 1bits in its design. Normal operation requires a supply voltage (Vsup) above 0.8V. There is a consumption of 500nAof quiescent current from it.

74AUP1G79GS,132 Features

Tape & Reel (TR) package
74AUP series
6 pins
1 Bits

74AUP1G79GS,132 Applications

There are a lot of Nexperia USA Inc. 74AUP1G79GS,132 Flip Flops applications.

• Reduced system switching noise
• Memory
• Safety Clamp
• Differential Individual
• Digital electronics systems
• Parallel data storage
• Balanced 24 mA output drivers
• Data transfer
• Frequency Divider circuits
• Asynchronous counter